Need help with 12 bit SAR ADC design

sar charge redistribution split series capacitor

Hello all!

I design a 12 bit charge redistribution ADC. I made an overview of many IEEE JSSC articles and books and stopped on Gilbert Promitzer IEEE article "12-bit Low-Power Fully Differential Switched Capacitor Noncalibrating Successive Approximation ADC with 1 MS/s".
But I have no some problems. Following the idea from this article I made binary weighted charge redistribution 8-bit MSB's capacitive array and resistors string DAC for last 4 bit's.
At first a proceed charge redistribution over this 8 binary weighted capacitors, an than I must resolve last 4 bits over the resistive DAC, but I little bit don't understand how to perform conversion of this last 4 bits over resistive DAC, how to connect capacitive DAC with resistive to perform conversion of last 4 bits?

Big thanks!

IEEE article you can find at following link

12-bit sar adc

You can find the analysis and how to do it in Allen and Holberg book on the chapter in ADC, he explains many different hybrid DAC topology for use in SAR ADC

sar adc with two capacitive dac

Hi Vladamir,
I think u can just connect the output node of the 4 bit resistive DAC to the unit C capacitor bottom plate and do the remaining bit trial .
Is your 8 bit capacitor DAC binary weighted. Why dont u split the CAP DAC into two and use coupling cap. This will reduce your overall design area as well as help in MSB bit trial settling as the MSB capacitors can be of much smaller in size. Refer Bakers book for this Scheme of splitting the DAC into two.

hope this helps
regards
Fred

sar adc gilbert promitzer

Its a very easy job... You have a weighted capacitance network say, C/2, C/4, C/8 and C/8... Now connect a similar network of capacitances C1/2 C1/4 C1/8 and C1/8 in series with the last capacitance arm (the bottommost C/8)... in this case, the last capacitance value must be modified so that when all switches are closed, the effective capacitance of the total network is "C"...

Added after 47 seconds:

Mail me if u have any problem... I am designing my SAR this way only...

Added after 1 minutes:

actually my method will replace ur resistive network with another capacitance network, thus minimizing your problems of resistance matching...

12-bit sar

hi, i have started my thesis right now..i have assigned 10 bit SAR, less than 1 mw , 100 ksps..fully in analog..i don't know spice and cadance... can anyone give me the spice schematic for simple or basic SAR...so that i can get some idea and proceed with that...please help me..

Re: sar adc gilbert promitzer

i m working on Charge redistribution DAC...Do u have any idea on it..please post it..

thnks
Piyush

Re: 12-bit sar

purush2007 said:

hi, i have started my thesis right now..i have assigned 10 bit SAR, less than 1 mw , 100 ksps..fully in analog..i don't know spice and cadance... can anyone give me the spice schematic for simple or basic SAR...so that i can get some idea and proceed with that...please help me..

Click to expand...

Did you get the schematicfor this? I'm having trouble finding it!

Re: sar adc gilbert promitzer

Umm don't you actually duplicate the original cap network, then add a series cap between the two banks to make the lower bank look like 1/n? Otherwise your scaling of smallest cap to biggest cap could get rather extreme. I don't have a reference handy, but I know this is a technique shown in many papers and textbooks.

Can someone explain to me how split series capacitor works in DAC? I understand the binary weighted capacitor charge redistribution DAC, but having difficulties to understand the split series type. Thanks.

Check this thesis.

Thank you very much.