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Checking connection in Layout in OrCad

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nitu

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Hi ..
I am presently involved in PCB board design and using OrCad for its layout. Chips that I am using are having very large number of pins and it takes a lot of time to just check layout connection visually. I would like to know is there is method or option which can help me in checking my final connection apart from visual check.

Some of my friends which are involved in chip design say that they some LVS checker tools which help them in debugging this problem.

Do we have any such thing in PCB design ?

Thanks for your help !!
 

I think,you can compare netlist in ORCAD BY REIMPORT THE NETLIST FILE again into the layout file.
If you use PCad2002 program,you can compare netlist easily by this steps:
1-open the layout file.
2-from Utils menue, choose compare netlist.



best regards
 

There is to way:

1)If you have a correct and exact schematic of your board circuit in OrCAD Capture, you can generate a layout netlist in OrCAD Capture, and update your board using AutoECO in Layout.

2) If you do not have an schematic, you can generate your board netlist (using OrCAD Layout Session-> File menu-> Export-> MAX ASCII Netlist) and see the netliast file in notepad or other test editor and check the net connectivity manulay. You may print the net connectivity part of the netlist file and use hard copy to check the net connectivity.

If you use Allegro Design Entry to design high pin boards, it is very easier to check the signal and component connectivity.
 

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