nitu
Advanced Member level 4
Hi ..
I am presently involved in PCB board design and using OrCad for its layout. Chips that I am using are having very large number of pins and it takes a lot of time to just check layout connection visually. I would like to know is there is method or option which can help me in checking my final connection apart from visual check.
Some of my friends which are involved in chip design say that they some LVS checker tools which help them in debugging this problem.
Do we have any such thing in PCB design ?
Thanks for your help !!
I am presently involved in PCB board design and using OrCad for its layout. Chips that I am using are having very large number of pins and it takes a lot of time to just check layout connection visually. I would like to know is there is method or option which can help me in checking my final connection apart from visual check.
Some of my friends which are involved in chip design say that they some LVS checker tools which help them in debugging this problem.
Do we have any such thing in PCB design ?
Thanks for your help !!