Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

problem with Active HDL 6.3

Status
Not open for further replies.

rockgird

Junior Member level 3
Joined
Apr 28, 2006
Messages
30
Helped
1
Reputation
2
Reaction score
1
Trophy points
1,288
Activity points
1,543
hii,
i m using , Active HDL 6.3 to write a program for subtractor. compilation is done properly but while cecking in waveform editor . m facin a strange problem . the binary input m giving is not getting celculated properly , the problem would be cleared wid this attached pic .
 

Hi rockgird, it would be better if you send the code you are compiling. It seems you are not assigning the output correctly.
What are the signals Bi1, Bi2, ... BiN?
Why are they in high impedance state?
The code would be of much help.

Regards,
 

hii ,

i had figured the problem out. actually the problem was with code only. i was givin wrong veriable name to the flag.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top