# How to do stability analysis of a common mode feedback loop?

1. ## How to do stability analysis of a common mode feedback loop?

Can anyone guide me how I can do a stability analysis of a common mode feedback loop? I want to plot the phase margin of that over PVT variations. Please help.

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2. ## Stability analysis

cut the loop at some point, add a probe instance "iprobe" from analoglib between the two points where u cut the loop, from analog enviroment choose stb for stability analysis , fill the required as if u r doing ac analysis "not as if, actually u r doing ac analysis", at select probe push select and select the probe u inserted.
simulate
from analog enviroment >results>direct plot, main form ,stb , "magnitude" and phase ,plot

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3. ## Re: Stability analysis

Hi ,
I have done the analysis but there is a problem. The circuit is unstable(I think) at 1GHz(design freq). What should I do to get it stable at 1GHz? I have tried different values for Rc, R and C but to no effect. Should I have to redesign the whole circuit?

4. ## Re: Stability analysis

Oops forgot the plot here it is.

5. ## Re: Stability analysis

Hi,

1) First, what is the intent of your main circuit? You have the input at gate of NMOS differential pair tied to gate of an NMOS load (positive feedback?)

2) You have shorted the output with a resistor (Why?).

3) For stability analysis, you have to keep Rc in place - the second picture shows that one of the Rc is missing.

4) In your common mode correction/detection circuit, do not use ideal current source. Use a transistor current mirror. This is important because the impedance of the tail current source affects the common mode response in your circuit configuration.

5) Instead of your current way of probing, I would insert a voltage source probe between the output of the CMFB circuit and the point where it is feeding to the gate of the PMOS current source load.

6) Is the compensation you add (R,C) at the input of the CMFB detection/correction differential pair helping you at all? Is that the location of the dominant pole for the CMFB loop? I guess not, most probably the dominant pole is at the output of the main circuit.

Bharath

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6. ## Stability analysis

i am little confused about ur circuit , u r using the cmfb for mirroring some current, u should first pass the current "ideal source" throught a the mirror branch , then copy this current to ur circuit (either CMfb and main circuit), also in ur circuit does the diode connected load good for cmfb, it should have low gain , so the cmfb will not precisely adjust ur cm to the Vref , i think u should use a diff. to single ended diff. pair .
a last question what is the name of ur main circuit.(is that some kind of buffer)

7. ## Re: Stability analysis

what about make an ideal CMFB and put it insted of ur circuit version then run stb and vary the gain of this ideal one tell u find the optimum gain to have min error and stable circuit at the same time
u can make the ideal one using verilog-a or try to find it in the libs of cadence "i think it is available "

8. ## Stability analysis

Well I am using the circuit as an LVDS transmitter. Its a commonly used circuit. I have to use a resistor to terminate as specified by LVDS standards. Its a differential circuit.
There is no NMOS load. It is also an input stage. Basically its acting like a switched current source.

Sorry for the pic. The Rc is still there but masked by the font.

I will try using a current mirror and see if it works fine.

Thanks to all for the reply.

9. ## Re: Stability analysis

5) Instead of your current way of probing, I would insert a voltage source probe between the output of the CMFB circuit and the point where it is feeding to the gate of the PMOS current source load.
Bharath[/quote]
Why insert a voltage source probe there is better?

10. ## Stability analysis

i am a little confused with your picture ,why LVDS output has no loading cap ,does it not contribute to the phase shift ?

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11. ## Re: Stability analysis

problems about the simulation of CMFB is always hot, maybe the teachers in univ should be responsible for this, they seldom taught the hand-on simulation tricks (maybe they just don't know,)

12. ## Re: Stability analysis

Originally Posted by suhas_shiv
Can anyone guide me how I can do a stability analysis of a common mode feedback loop? I want to plot the phase margin of that over PVT variations. Please help.
simulate the loop gain by add a source in the loop

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