vladimir1984
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Hello there!
I have a task to design SAR ADC with 12 bit resolution. Now I use charge redistribution SAR ADC.
Is it possible to achieve 12 bit resolition with INL less 1 LSB and DNL less 0.5LSB with this archotecture? Or I need trimming, calibration, digital error corection and so on... I use 0.18um BiCMOS technology. Now, I have bad Monte Carlo process & mismatches results, DNL up to 4LSB.
And one problem more, without using an split capacitive array with attenuator capactor I'll have a huge die area, but using spliting I have worse results than without.
Can anybody help or give some tipps or advise!!!
Thanks
Best regards
I have a task to design SAR ADC with 12 bit resolution. Now I use charge redistribution SAR ADC.
Is it possible to achieve 12 bit resolition with INL less 1 LSB and DNL less 0.5LSB with this archotecture? Or I need trimming, calibration, digital error corection and so on... I use 0.18um BiCMOS technology. Now, I have bad Monte Carlo process & mismatches results, DNL up to 4LSB.
And one problem more, without using an split capacitive array with attenuator capactor I'll have a huge die area, but using spliting I have worse results than without.
Can anybody help or give some tipps or advise!!!
Thanks
Best regards