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    How "tie-hi" "tie-low" cells work on ESD problem?

    Hi all,


    Can any body tell me how "tie-hi" "tie-low" cells works on ESD problem. And I also want the circuit digram of these cells


    Thanks in advance


    Rahul

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    tie high cell

    These are one of the standard cells.

    Tie High is for Vdd, where if any cell wants Vdd connection then autoplace and route would select this cell by itself, as its automated.

    Similarly Tie Low is for Ground, not sure of how they come in picture to reduce ESD.


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    tie hi

    these are sort of the special cell that can be used in later part of the design design to connect certain signal to HIGH or low values



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    what are tie cells

    they r used to avoid connecting the gates of the transistor directly to vdd or gnd.

    For Tei low, it is simply a diode connected pmos (its source connected to vdd and source to the gate of nmos transistor), the nmos transistor has it source connected to ground and the drain to transistor u want to connect its gate to ground.
    I really don't know the role of sizing of both transistors.


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    tie-high tie-low cells

    Tie high and tie low is used for latch up problem, I think gate should not connect to power/gnd directly.



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    tie high tie low

    Quote Originally Posted by wkong_zhu
    Tie high and tie low is used for latch up problem, I think gate should not connect to power/gnd directly.
    Not latch up, it is used for ESD problems



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    tie-hi cell

    Hi eng_semi,

    I didn’t get your point “For Tei low, it is simply a diode connected pmos (its source connected to vdd and source to the gate of nmos transistor), the nmos transistor has it source connected to ground and the drain to transistor u want to connect its gate to ground.”..

    It would be greatful if Elaborate your explanation..

    Thanks



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    tie low cell

    Hi,

    I don't know why tie cell can be used for ESD. Basically, we add some special circuit on pad for ESD protection. Tie cell is used for DFT, because if we directly connect the inputs of std cell to 1'b1 or 1'b0, it will cause some issues for DFT



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    tie cells

    The historical use of Tie-Lo and Tie-Hi cells is almost as much emotional as it is secular.

    The reason I say this is that some people use them religiously without thought as to why. Depending on your process and your design they may or may not be necessary. Most people do not know why they are used.

    ESD and Reliability are the right answer. In some processes, the gate oxide is very delicate and sensitive relative to the voltage levels of the chip. That means for any node with a gate tied to a low impedance, such as a GND or VDD, the voltage on the gate is fixed...but what happens if the voltage on the drain or source experienced a surge, over a short period of time, well after enough surges, your oxide reliability fails. Generally these surges are fast impulses, either ESD or ground bounce or some other fast transient impules, because if it was DC...then the chip would be operating outside the limits of the process.

    So how does the tie-lo/Hi work, it works by creating a DC level path but a high impedance AC path on the gate oxide, this allows the voltage level on the gate to spike up or down, with voltage surges on its drain and or source, and even though these voltage spikes are capacitively divided between all the nodes, because the gate voltage is allowed to follow or track surges on drains/sources, than the voltage across the delicate oxides are kept within more tolerant levels than if the gate had been hard tied to a low impedance GND/PWR.

    This is particularly critical on CDM (charge Device Model) ESD type events for IC's.

    For almost this exact reason, you see a lot of 65nm and 45nm (even some 130 and 90nm) process that do not allow LVT decoupling caps with oxides tied directly to a power or ground terminal (gate leakage problems aside...though that is also a factor).

    They are not always needed and do tend to take up more area. Know your process, your design and the conditions for your design to determine if you need them or not...when in doubt however, I would recommend using them.

    As for how they are designed, there are many formats, the most common being a large resistor in series with the gate, others involving diodes or secondary transistors, etc.

    SRFTech


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    tie low

    hey rahul,

    These Tie high n Tie Low r simple diodes as Asha explained well...

    they help in avoiding ESD problems...in such a way dat.......just imagine as these diodes r in reverse biased like state, as charge approching results in increase in Depletion region....and then after supplying regular voltage...upto certain extent Tie cells acting as reverse bias...if voltage across Tie cells node increases, it allows current to flow to Gnd....its quite simple.......



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    tie on cell

    Tie Hi and Tie Low cells are used in the first place where the gate of the standard cell has to be connected to either power or ground. Now it is never recommended that the gate be connected directly to power and ground nodes directly as with supply glitches can damage the damage. They add tie cells which are nothing but resistors to make sure that the supply/ground is connected thru them.

    Also as a general promotion there is a new website started for discussion forum called "www.rtl2gates.com". Please check it out.

    Thanks
    D


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    tie cell circuits

    Hi,

    can you suggest the advantages of inserting the tie high cells and tie low cells into the design after placing the instances.? rather than inserting them into the design during logic design.?

    Thanks,
    Vlsi123

    Added after 17 minutes:

    Just smal correction in the above, during 'logic sythesis' not logic design.



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    Re: Tie-hi Tie-low cell

    What are constant cells?
    can any one give reference to any papers or docs regarding the same and for Tie-hi Tie-low cell.


    Thanks in advance.



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    Re: Tie-hi Tie-low cell

    attaching tie hi ckt.. i am not able to understand how the nmost transitor enable the pmos transistor,
    I know only know that nmos connection is like back to back connection of two diodes,, but dont know hw thy will come in to fwd bias state and enables the pmos transistor



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    Tie-hi Tie-low cell

    Do u have the size ?



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    Re: Tie-hi Tie-low cell

    You may get more information about tie-hi/lo cells from FOUNDRY!



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