jutek
Full Member level 4
slew rate enhancement
hello
i've met this problem during simulation.
the circuit is in ntype.png file
this is symetrical ota (M17-M24) with slew rate enhancement circuit (M25-M31).
at wth_out_curr.png M25 current is presented.
at sre_curr.png M31 and M32 currents are presented.
Slew rate enhancement circuit doesn't influence on ac response (ac.png)
the main problem is presented at both.png It's transient response, when the ldo's output is programmed from 0.8 to 1.4V It should be fast (1us), overshoot,undershoot should be less than 30mV
The yellow curve is response without sre ciurcuit. As you can see at wth_out_curr.png M25 doesn't give much current to drive power device's capacity.
I've expected a better response (pink one) cause it drives big currents (see sre_curr.png). It doesn't happen (why???)
The second thing is overshoot. How can i decrease it? by improving phase margin, i know. now, phase margin is poor (30deg) I can lower zero increasing output capacity, cause the time response will be higher.
I can't move the second pole higher cause i would have to use more current in the opamp and the main spec is low current working.
What else i can do to win with these trade-offs??
regards
hello
i've met this problem during simulation.
the circuit is in ntype.png file
this is symetrical ota (M17-M24) with slew rate enhancement circuit (M25-M31).
at wth_out_curr.png M25 current is presented.
at sre_curr.png M31 and M32 currents are presented.
Slew rate enhancement circuit doesn't influence on ac response (ac.png)
the main problem is presented at both.png It's transient response, when the ldo's output is programmed from 0.8 to 1.4V It should be fast (1us), overshoot,undershoot should be less than 30mV
The yellow curve is response without sre ciurcuit. As you can see at wth_out_curr.png M25 doesn't give much current to drive power device's capacity.
I've expected a better response (pink one) cause it drives big currents (see sre_curr.png). It doesn't happen (why???)
The second thing is overshoot. How can i decrease it? by improving phase margin, i know. now, phase margin is poor (30deg) I can lower zero increasing output capacity, cause the time response will be higher.
I can't move the second pole higher cause i would have to use more current in the opamp and the main spec is low current working.
What else i can do to win with these trade-offs??
regards
