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Xilinx error: CLOCK does not clock any primary output

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L_E_D

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I am using xilinx, for my assignment, i got the following warnings which I can't understand....any kind soul can explain to me please.. When I start implementing my design...the final report show this....what went wrong?

WARNING:CLK Net:Inst_long_counter/count_int<26>
WARNING:Timing:2665 - CLOCK does not clock any primary output
WARNING:Timing:2666 - Constraint ignored: OFFSET = IN 10 ns BEFORE COMP "CLOCK";
WARNING:Timing:2665 - CLOCK does not clock any primary output
WARNING:Timing:2666 - Constraint ignored: OFFSET = OUT 10 ns AFTER COMP "CLOCK";
 

Re: help~~

I think the path from input to output does not contain the influence of clock, that is the clock signal path is broken somewhere. You carefully check the output signal assignment statements, they might not have the clock influence. That is output signal changes irrespective of clock.
 

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