delay
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Hello Gurus,
I wrote a state machine in VHDL and then simulated it using ISE and ModelSim in three different ways within ISE:
A) New Source -> VHDL Test Bench, entered test vectors in the process statements
B) New Source -> Test Bench Waveform, generated a behavioral .vhw file from wave forms that I developed. I saved .vhw as a .vhd and executed it as testbench
C) Launched ModelSim Simulator by selecting the source file, once the tool came up entered stimuli manually and ran ModelSim
Now all three ways should give the same results since I have the same set of inputs in all three cases, however, I see that B and C give same output waveforms so does A but when I turn on the current state and next state signals they are exactly same in case A. I would expect that the next state signal be ahead of current state signal one clock cycle, i.e., the current state should be delayed one cycle but both signals are exactly same as if they are the same. This does not happen in cases B and C where there is one cycle latency between the two state signals. While the outputs are correct and are at the right time, the current state and next state signals being the same bothers me. I am also concerned about generating testbench file using VHDL Test Bench option in ISE because of the results I obtained.
Please share your experience regarding this problem. Which method of the three you find most accurate.
Thanks.
Delay
I wrote a state machine in VHDL and then simulated it using ISE and ModelSim in three different ways within ISE:
A) New Source -> VHDL Test Bench, entered test vectors in the process statements
B) New Source -> Test Bench Waveform, generated a behavioral .vhw file from wave forms that I developed. I saved .vhw as a .vhd and executed it as testbench
C) Launched ModelSim Simulator by selecting the source file, once the tool came up entered stimuli manually and ran ModelSim
Now all three ways should give the same results since I have the same set of inputs in all three cases, however, I see that B and C give same output waveforms so does A but when I turn on the current state and next state signals they are exactly same in case A. I would expect that the next state signal be ahead of current state signal one clock cycle, i.e., the current state should be delayed one cycle but both signals are exactly same as if they are the same. This does not happen in cases B and C where there is one cycle latency between the two state signals. While the outputs are correct and are at the right time, the current state and next state signals being the same bothers me. I am also concerned about generating testbench file using VHDL Test Bench option in ISE because of the results I obtained.
Please share your experience regarding this problem. Which method of the three you find most accurate.
Thanks.
Delay