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What is CMOS Latch up and how to prevent it?

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malind

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What is CMOS latch up? Why does it occur and what measures can we adopt to prevent it?
 

Re: CMOS Latch up

Low resistence between power signals is called latchup
 

CMOS Latch up

Latch-up pertains to a failure mechanism wherein a parasitic thyristor (such as a parasitic silicon controlled rectifier, or SCR) is inadvertently created within a circuit, causing a high amount of current to continuously flow through it once it is accidentally triggered or turned on. Depending on the circuits involved, the amount of current flow produced by this mechanism can be large enough to result in permanent destruction of the device due to electrical overstress (EOS).
 

Re: CMOS Latch up

Hello.

I hope attached file will be helpful to you.

Y.C
 

    malind

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Re: CMOS Latch up

two parasitic transistors exist in the substrate of CMOS, unwanted signal like noise or any other small voltage can trigger this transistors and would vreate a direct path from Vdd to VSS which would results in burn out of chip thats y we do N-tapping for p transistor and p-tapping for n transistor.
 

Re: CMOS Latch up

the paper may be usefull for you
 

Re: CMOS Latch up

the following paper will give you some advise for testing
 

Re: CMOS Latch up

resistor parasitics.
 

Re: CMOS Latch up

I think it will be clear to u bye the following pdf.
 

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