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[Need help]Verilog simulation models problem

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cheelgo

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Hi,
I am not that familar verilog simulation models,

------
padlib.v
------
module padlib (...);
input ...;
output ..;

wire ...;

...

...

`ifdef cve
buf #0.001 (...);
`else
or #0.001 (...);
`endif

endmodule

Question:
if I only wanna force this model use cve part, HOW can I configure,
can I use set cve true

somebody can help.
thanks in advance?
Cheelgo
 

Any simulator has the optional of "+define+macro...". You can find the detail information of the vcs/ncverilog/ncsim/modelsim/... -help.
 

Hi,

I did not quite understand your question. But if you are trying to configure
the verilog module, use compiler primitives like "#define cve".

RP,
 

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