# Design a latch comparator consider input voltage

1. ## Re: Design a latch comparator consider input voltage

I have several question for this schematic to deisgn:

1.If I want to design dc 0.9v compare with ramp signal ,the M1 & M2 dc voltage should be set in 0.9v or Vdd/2 initially?

2. the net3 should be set in dc Vdd/2 or other dc level voltage when design?

3. Should be (W/L) of M7 & M9 should be the same then to adjust Vg7 & Vg9 in order to reduce systematic offset?

4.the net1 voltage should be as low as possible (higher than Vth7)?

5.if remove M4&M5,net1=net2=1V; if remove M3&M6,net1=net1=1v,but
when I merge them(M3&M4;M5&M6),the net1 voltage is drop to 0.85V? why?

6.If i want to look the gain,should I watch small signal gain(use .ac? ) or dc gain (M1&M2 send dc voltage and use .tf?)?

7.when i want to see offset ,input should be set Vdd/2?

schematic here

thank

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2. ## Re: Design a latch comparator consider input voltage

1 first you must know the signal's fast frequency and the resolution.
2 M1&M2 DC voltage is better to set about 0.9v.
3 the net3's DC voltage not need to set a accurate voltage.
4 M7&M9 is not the same type MOS, they can,t match.
5 if you make this circuit to latch, i don't know to see it's gain.
6 you should take care the ratio of M4/M3 or M5/M6.it <1 or >1 is different.

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3. ## Design a latch comparator consider input voltage

1 the Book "introduction to CMOS OP-AMPS and Comparators " u can reference.
2 If you design it's output like schmitt triggers,you'd better analyze the Volgate trigger.
3 Care for you application.

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4. ## Re: Design a latch comparator consider input voltage

I have know some thing
very appreicate jerryzhao!!

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