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Error when running testbench file by ModelSim

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test_out

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How can I solve this?

When I run the testbench file by ModelSim I got this error:

# ** Error: E:/Mem Control/testbench/test_lib.v(82): near "always": expecting: LIBRARY CONFIG

at this code line:

always @(posedge clk)
if(wb_cyc_i) cyc_cnt = cyc_cnt + 1;


How can I solve this?
 

Re: How can I solve this?

Obviously the your want one dff and an adder to do your job.
But the use of "posedge" tell compiler this is a dff.
So, can you put an adder in your dff?
compiler cannot find a dff with an adder in the library.

You may use following codes:

always @(posedge clk)
if(wb_cyc_i)
dout <= cyc_cnt;

always@(dout)
cyc_cnt<=dout+1;
 

Re: How can I solve this?

maybe can try this:

always @(posedge clk)
if(wb_cyc_i) cyc_cnt <= cyc_cnt + 1;
 

Re: How can I solve this?

johnz said:
maybe can try this:

always @(posedge clk)
if(wb_cyc_i) cyc_cnt <= cyc_cnt + 1;
Click to expand...

hi,johnz,
Are u sure this can lead to the synthesis of a dff and an adder?
 

How can I solve this?

I think the adder and the DFF should be seperate! I agree the point of laglead.
 

Re: How can I solve this?

laglead said:
johnz said:
maybe can try this:

always @(posedge clk)
if(wb_cyc_i) cyc_cnt <= cyc_cnt + 1;
Click to expand...

hi,johnz,
Are u sure this can lead to the synthesis of a dff and an adder?
Click to expand...

Hi laglead,
I just want to try another coding,
you can thynthesize it by yourself, take look whether their results are same.
 

How can I solve this?

the segment of your code is correct! it's not the root cause of this problem.
 

Re: How can I solve this?

I dun see any problem with the coding too. It should work with simulations.
Prehaps, you can try to check the syntax.

Cheers
 

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