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why vdsat can be lower for submicron cmos process? eg. vdsat

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lijulia

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vdsat velocity saturation

=100mv for 0.18um cmos process, because normally we design for vdsat=200mv.
 

vdsat in strong inversion

Please go through any MOEFET physics books,u will come to know.

Read velocity saturation in that,and look at the curve,it resembles as our Drain current.

As we reduce the power supply for DSM. we also reduce VDSAT,i.e., we will have strong inversion for low voltage,as we have reduced channel length.

This is vague explanation.Also go through any book.
 

vds<vdsat why in saturation

lijulia said:
=100mv for 0.18um cmos process, because normally we design for vdsat=200mv.

I have a doubt on your words: "can be" or "normally should be"?
Even for 1-um process the Vdsat can be 100mv. If Vgs-Vth<100mv your transistor is still in saturation.
In submicron cmos, we don't want velocity saturation effect. So, Vdsat should normally be 100mv, or even smaller.
 

Re: why vdsat can be lower for submicron cmos process? eg. v

laglead said:
In submicron cmos, we don't want velocity saturation effect. So, Vdsat should normally be 100mv, or even smaller.
hello laglead,
i wanted to know what is Vdsat realation with velocity saturation ? (i.e. Do u mean that if it got to a certain value of vdsat then we are in v.saturation)
also i have another question why not working in v.saturation ?
i was also wondering dont we usually design for some min. Vdsat value sau 150mV , or we can be below 80mV?
regards,
a.safwat
 

Re: why vdsat can be lower for submicron cmos process? eg. v

I think he is confused.

Vsat is velocity saturation in short(0.5 to 0.25 micron) and narrow(0.18 to 0.13 micron) channel transistors. It has nothing to do with VDSat. Vsat is due to the E-field from drain acting on the electrons in the channel and source when VDD is applied to the drain. Therefore constant electron mobility no longer holds true! It varies with E-field strength! This curve in Vsat versus channel length or with VDD is the evidence to show that Vsat varies with E-field. The narrower the channel gets, the greater the E-field impact on Vsat.

VDSat is Saturation VDS. This is the knee voltage where the transistor transits from strong inversion to saturation.
Do not confuse Vthreshold with VDSat.
When you see the VDS versus ID transconductance curve, the curves for increasing VGS are already drawn when VDS is higher than Vthreshold, in other words, all plots drawn in this VDS vs. ID transconductance curve are drawn in strong inversion.
Many people still think VDSat = Vthreshold which is wrong!
 

Re: why vdsat can be lower for submicron cmos process? eg. v

Hi ,
Normally we dont consider the effect of Velocity saturation in Analog Ckts as we dont go for minimum length devices.But the explanation is perfect and if VDSAT is at .2v then the device may be in saturation(velocity) as the E field is 1V/um
if this is the case we can go for low VDsat as there is no more sq. law relationship bet. i and V and that is linear.so Gm will be reduced by factor 2 but no constraints on inpt. signal amplitude.
 

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