Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

assign statement in netlist

Status
Not open for further replies.
omid219

omid219

Advanced Member level 4
Joined
Feb 2, 2005
Messages
117
Helped
5
Reputation
10
Reaction score
1
Trophy points
1,298
Location
Malaysia
Activity points
988
do_xform_fix_multiport_nets

Hi,

I'm using PKS from cadence as synthesis tool. In the generated netlist, there are some "assign" statements. I know how to get rid of them in synopsys' design compiler or cadenc's rtl compiler. But I don't kknow how can I get rid of "assign" statements in PKS? Any idea how can I fix this?

Thanks
 

Hi,
two reasons cause assign statement in netlist.
1. two or more poort connected to same net.
2 . a port directly connected to 1'b0 or 1'b1

you can try:

for PKS 5.2 :

set_global multiport_fix_buffer_const_nets true
foreach module [ find -modules -hierarchical ] {
set_top_timing_module $module
set_current_module $module
do_xform_fix_multiport_nets
}
set_top_timing_module $top_module
set_current_module $top_module

for PKS 4.2 or before version :

foreach module [ find -modules -hierarchical ] {
set_top_timing_module $module
set_current_module $module
do_xform_fix_multiport_nets -fix_constant_ports
}
set_top_timing_module $top_module
set_current_module $top_module
 

    omid219

    omid219

    Points: 2
    Helpful Answer Positive Rating
Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top