The digital design flow for Cadence

Hi guys ..

I would like to know the exact digital design flow for cadence .. starting from HDL down to GDSII ..

cadence asic design flow

Hi,
they have their own tutorial links which tells you the complete flow using cadence tools. its available at

**broken link removed**

under the "introduction to ASIC implementation"

hope this helps.

site crete cadence

hi,
rtl -> rtlcompiler -> first encounter -> gps -> nanoroute

cadence synthesize power plan

linuxluo said:

hi,
rtl -> rtlcompiler -> first encounter -> gps -> nanoroute

Click to expand...

what's (First Encounter) for ?
GPS ?
Nanoroute ?

are all these tools embedded in SoC Encounter ?

and where can I use a tool like Assura or Diva ?

cadence design flow

chek this site
**broken link removed**

fe gps cadence

FE (First Encounter):
- Prototyping tool --> floor plan, power plan,...

GPS (Global physical synthesis):
- Use the same keyword of "global synthesis" from RTL Compiler.

NanoRoute:
- Router (global route + detail route)
----------------------------------------------------------------------------
SOCE 5.2 = FE + RTL Compiler + sRoute + NR + crosstalk analysis (Celtic) + ...

-----------------------------------------------------------------------------
SOCE does not contain sign-off DRC/LVS features.
------------------------------------------------------------------------------

Cadence RTL-to-GDSII flow:
- 1) synthesisDesign
- 2) planDesign + APP(automatic power plan)
- 3) placeDesign
- 4) clockDesign
- 5) globalDetailRoute (routeDesign)
------------------------------------------------------
- 6) ecoDesign

introduction cadence design flow

sree205 said:

Hi,
they have their own tutorial links which tells you the complete flow using cadence tools. its available at

h**p://crete.cadence.com

under the "introduction to ASIC implementation"

hope this helps.

Click to expand...

The CRETE website is no longer supported. and I can't get that paper, can you kindly upload it here?

Thanks,
Ahmad,