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back-to-back and NOT back-to-back std. cell placement

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eexuke

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Dear all,
If I have enough area for my chip,what is the pros and cons of back-to-back vs. NOT back-to-back standard cell placement?

Thanks in advance!
 

as far as i know, abutting is used to make sure that the same power stripes are used for 2 rows of std. cells. this is to minimize the power dissipation.

i think ASIC book by sebastian smith explains this.
 

sree205, are you sure?
from the point of power dissipation, though, the power stripe width of std cells is fixed(when design std cell, the load of the power wire will be considered, so how much of std cells can share the power wire is fixed at most),i think it is not useful as you said, becasue you can use thinner power wire when you use the power stripes only for one row of standard cells.
i think the main reason is reducing area, because the space between two power stripes is necessory.
in addition, i think how you place the standard cells depends on the library.for example,if the library is not designed to back-to-back placement, you cannot do that.
 

I agree with tarkyss.
However, if I have enough chip area and routing resources, back-to-back has no too much difference compared with NON back-to-back,right?
 

i might have been confused between power stripes and power rails. i do have a question. taking two cases into consideration, if we have a power rail abutting layout in one and non-abutting in another, apart from reduction in area, both of them will dissipate the same power?

yes, i do agree with tarkyss that its dependant on the library thats provided. but in most of the cases, it is provided, isn't it ?
 

sorry, i use power stripe wrongly,
for std cell, it is power rail
I think the results are almost the same, because the power wire width of std cell is fixed, so the current it can provide is fixed, for example , it can drive 1000 inverters, if non-abutting, it can drive one row of 1000 inverters. for abutting, it can drive two rows, but each rows only have 500 inverters at most.
in most cases library can support abutting
 

Does anyone think about the hold-time issue in back-to-back style?
If you P&R flip-flop, you should take care of this issue.
If the data-out from the first flip-flop to the second one is too fast, it will corrupt the data capture of the second flip-flop, because the second flip-flop need time to capture the data. It is the hold time.
 

laglead said:
Does anyone think about the hold-time issue in back-to-back style?
If you P&R flip-flop, you should take care of this issue.
If the data-out from the first flip-flop to the second one is too fast, it will corrupt the data capture of the second flip-flop, because the second flip-flop need time to capture the data. It is the hold time.
This issue must be taken by both synth. tool and after P&R. It does not relate to back-to-back and not back-to-back placement here.
 

can any one help me to find project at control using labview
 

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