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  1. #1
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    tiny verilog question:)

    what does this mean:

    "verilog is an interpretive language"...?

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    tiny verilog question:)

    an interpretive language is one that isnt compiled. like in MATLAB you write the script and then run the script and it runs one line at a time and if there is an error, it stops running. but in C you write your code and then compile, which checks the errors and if there are no errors, the linker gives you the exe file. and then you run the program. so C is a compiled language and MATLAB is an interpretive language. generally compiled languages are faster than interpretive languages

    but im not sure if this statement is correct. infact verilog isnt a computer programming language at all. verilog is a hardware descriptive language and HDLs are quite different from computer programming languages. where did you get this statement from??????



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    tiny verilog question:)

    i read that it is so when i was reading up on PLIs.

    http://www.project-veripage.com/history.php



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    Re: tiny verilog question:)

    verilog is not interpreter based, it is compiled - I think this is a wrong statement - u should send a mail to the author and ask him directly what he meant -
    ag



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    Re: tiny verilog question:)

    well, i read in the book of Douglas Smith (HDL chip design)
    i should ask him about that ...right?



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  6. #6
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    tiny verilog question:)

    Verilog is not interpreted or compiled. It's a hardware description language. It is up to the simulator how it wants to genreate it's internal representation of the code. Some environments use the platforms native machine code for fast simulation.



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