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    Basic MOS question

    Whats the main reason for using polysilicon instead of Metals for gates?

    I remember reading somewhere its because of the alignment problems of source/drain wrt metal? I am not sure self-aligment process available now also have this problem with metals?

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    Re: Basic MOS question

    hi,
    The primary criterion for the gate material is that it is a good conductor. Highly-doped polycrystalline silicon is an acceptable, but certainly not ideal conductor, and it also suffers from some more technical deficiencies in its role as the standard gate material. There are a few reasons why polysilicon is preferable to a metal gate:

    The threshold voltage (and consequently the drain to source on-current) is determined by the work function difference between the gate material and channel material. When metal was used as gate material, gate voltages were large (in the order of 3V to 5V), the threshold voltage (resulting from the work function difference between a metal gate and silicon channel) could still be overcome by the applied gate voltage (i.e. |Vg - Vt| > 0). As transistor sizes were scaled down, the applied signal voltages were also brought down (to avoid gate oxide breakdown, hot-electron reduction, power consumption reduction, etc). A transistor with a high threshold voltage would become non-operational under these new conditions. Thus, poly-crystalline silicon (polysilicon) became the modern gate material because it is the same chemical composition as the silicon channel beneath the gate oxide. In inversion, the work-function difference is close to zero, making the threshold voltage lower and ensuring the transistor can be turned on.
    In the MOSFET IC fabrication process, it is preferable to deposit the gate material prior to certain high-temperature steps in order to make better performing transistors. Unfortunately these high temperatures would melt metal gates, thus a high melting point material such as poly-crystalline silicon is preferable to metal as gate material. However, polysilicon is highly resistive (approximately 1000 times more resistive than metals) which reduces the signal propagation speed through the material. To lower the resistivity, dopants are added to the polysilicon. Sometimes additionally, high temperature metal such as tungsten, titanium, cobalt, and more recently nickel, is layered onto the top of the polysilicon (as a side effect of layering metal on the source and drain contacts) and alloyed with the polysilicon to decreases the resistivity. Such a blended material is called silicide. The silicide-polysilicon combination has better electrical properties than polysilicon alone and still does not melt in subsequent processing. Also the threshold voltage is not significantly higher than polysilicon alone, because the silicide material is not near the channel. The process in which silicide is formed on both the gate electrond and the source and drain regions is sometimes called salicide, self-aligned silicide.
    When the transistors are extremely scaled down, it is neccessary to make the gate dielectric layer very thin, around 1 nm in state-of-the-art technologies. A phenomenon observed here is the so-called poly depletion, where a depletion layer is formed in the gate polysilicon layer next to the gate dielectric when the transistor is in the inversion. To avoid this problem a metal gate is desired. A variety of metal gates such as tantalum, tungsten, tantalum nitride, and titanium nitride, usually in conjunction with high-k dielectrics. An alternative is to use fully-silicided polysilicon gates, and the prosess is refered to as FUSI.

    In found this information in:
    http://en.wikipedia.org/wiki/MOSFET

    Regards.


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    Re: Basic MOS question

    Unfortunately these high temperatures would melt metal gates, thus a high melting point material such as poly-crystalline silicon is preferable to metal as gate material.
    Melting the metal gate in the annealing process is definitely one of the problem... so some people proposed the "last gate" process, in which they made the metal gate in the last step, after all annealing. In conclusion, dual-metal gate is desirable: metals with suitable work functions can be selected to adjust the threshold voltage, and poly-depletion problem would be avoided to improve the EOT. The difficulties are in the fabrication processes.



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    Re: Basic MOS question

    In olden days, we used a metal, but now poly.



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    Re: Basic MOS question

    Maybe in the futhur it will come back to metal-gate.
    For 45nm or smaller size.


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    Re: Basic MOS question

    I like the answers I see here. Can anyone tell me how the so-called "low-threshold" MOSFETs are physically different from the regular ones?



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    Re: Basic MOS question

    Quote Originally Posted by matchasm
    I like the answers I see here. Can anyone tell me how the so-called "low-threshold" MOSFETs are physically different from the regular ones?
    hello,
    i am not sure but i guess by increaasing the doping under the channel [ n doping for NMOS] , as this will decrease the needed potential for inversion, i think this may be the way how depletion MOS are done?
    regards,
    a.safwat



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    thank you guys!!!

    Thanks a lot for the reply guys.

    I have another basic question.

    What are the solutions for reducing the Hot-electron effect?
    * increasing the oxide thickness
    * LDD structure -- I am not sure how this helps in reducing? if someone can explain it will be helpful.

    How different is hot-electron effect from hot-hole effect?



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    Re: thank you guys!!!

    Quote Originally Posted by ranair123
    Thanks a lot for the reply guys.

    I have another basic question.

    What are the solutions for reducing the Hot-electron effect?
    * increasing the oxide thickness
    * LDD structure -- I am not sure how this helps in reducing? if someone can explain it will be helpful.

    How different is hot-electron effect from hot-hole effect?
    * increasing the oxide thickness
    this is impossible now, because the size of mosfet is smaller and smaller ,so the oxide thickness is decreasing

    * LDD structure

    it is not only can reduce Hot-electron effect ,but also can increase the breakdown voltage of the device

    the reason is:

    the intensity of the electric field is proportion to the doping level of a pn junction .
    hign level doped pn junction always has high peak electric field , so ldd(light doped
    drain) can decrease the electric field ,and so the carrier can not acquire enough energy
    to enter the gate oxide.

    hot carrier effect for a pmos is not as serious as the nmos. because the carrier of a pmos is hole,the barrier between the gate oxide and hole is higher than electron,so it need more energy to enter the oxide.


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    Re: thank you guys!!!

    Quote Originally Posted by jeff_zx
    * increasing the oxide thickness
    this is impossible now, because the size of mosfet is smaller and smaller ,so the oxide thickness is decreasing
    -- I guess High K dielectrics might help in increasing the thickness to get the same current level as SiO2??



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    Basic MOS question

    but maybe in the futrue, we must use metal gate again.



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    Re: Basic MOS question

    with the develop of process ,maybe use matal gate in the futher



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    Re: Basic MOS question

    hot electrons will get enough energy from drain to source electro field and break into sili-oxide and generate traps, which will de-grade the performance of mos transitor, so obviously increase the gate oxide quality is one of the solution, to grow the gate oxide under very strict humidity and atmosphere control shall give us a better Gate-oxide, I guess. Actually we are using this method to improve our flash memory cell reliability.



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    Re: Basic MOS question

    hey thanks a lot!
    it really helped a lot !
    but can someone please tell me how come the threshold voltage increases with use of metal?
    i think its other way round ri8?

    ---------- Post added at 15:33 ---------- Previous post was at 15:23 ----------

    also what i think is:
    to reduce the hot-electron effect,
    we need to replace SiO2(dielectric constant: 3.9) gate oxide by high k dielectrics.(like how intel is replacing SiO2 with Hafnium dioxide(dielectric constant=20) in order to achive the same value of gate capacitance still maintaining the gate oxide thickness...)

    also,
    making use of clock tree synthesis is also gud idea of reducing the hot electron effect..
    hence,
    the current trend is to:
    replace gate material from polysilicon to metal,
    replace sio2 oxide with hafnium oxide,
    replace cmos by BiCMOS,
    replace aluminium by copper in metal wiring interconnects..(as copper has lesser sheet resistance than aluminium,hence interconnect capacitance is reduced due to this.)


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