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  1. #1
    Newbie level 2
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    need advice and help!!!

    hello ! i,m newbie in this forum and vhdl programming...
    so i hope somebody can help me to correct my programming and
    give me some advice..
    i was trying to make a control unit between UART and AES core... i make a little
    moddification of the source code that i download from open cores...
    bellow is my control unit that i try to write but i don't know how to check that every path receive the data that should receive...plz help me


    --Beta version

    library IEEE;
    use IEEE.std_logic_1164.all;
    use IEEE.std_logic_arith.all;
    use IEEE.std_logic_unsigned.all;


    entity final_aes128 is
    port(
    RxD : in Std_Logic;
    TxD : out Std_Logic;
    Reset : in STD_LOGIC;
    done : out std_logic;
    CLK : in STD_LOGIC

    );
    end final_aes128;


    architecture final_aes128_arch of final_aes128 is

    --AES signals
    signal AES_start, AES_outrdy, AES_mode,load: std_logic;
    signal AES_DataOut : std_logic_vector(127 downto 0);
    --signal counter_DataIn, counter_KeyIn : std_logic;

    --receive and transmit signal
    signal UART_Outrdy, UART_Rx, UART_Tx, UART_Tdone, UART_TbufE : std_logic;

    --input AES core signal
    signal AES_key: std_logic_vector( 127 downto 0);
    signal AES_data: std_logic_vector( 127 downto 0);

    signal UART_DataIn, UART_DataOut : std_logic_vector(7 downto 0);
    signal En_Encryp : std_logic;

    --state signal
    signal state : std_logic_vector(3 downto 0);
    signal sub_state : std_logic_vector(3 downto 0);



    component clk_divider
    port (
    SysClk : in Std_Logic; -- System Clock
    En_Encryp : out Std_Logic; -- Control signal
    Reset : in Std_Logic -- reset
    );

    end component clk_divider;


    component miniUART
    port (
    DataRdy : out std_logic;
    SysClk : in Std_Logic; -- System Clock
    Reset : in Std_Logic; -- Reset input
    --CS_N : in Std_Logic;
    RD_N : in Std_Logic;
    WR_N : in Std_Logic;
    RxD : in Std_Logic;--assign pin to W8
    TxD : out Std_Logic;--assign pin to D15
    TBufE : buffer std_logic;
    TDone : out std_logic;
    DataIn : in Std_Logic_Vector(7 downto 0);--receive output from AES core
    DataOut : out Std_Logic_Vector(7 downto 0));--send data to AES core
    end component miniUART;


    component aes128_fast
    port(
    clk : in std_logic;
    reset : in std_logic;
    start : in std_logic; -- to initiate the encryption/decryption process after loading
    mode : in std_logic; -- to select encryption or decryption
    load : in std_logic; -- to load the input and keys.
    key : in std_logic_vector(127 downto 0);
    data_in : in std_logic_vector(127 downto 0);
    data_out : out std_logic_vector(127 downto 0);
    done : out std_logic );
    end component aes128_fast;


    begin

    U_clkdiv : clk_divider
    port map(Clk, En_Encryp, reset);

    U_UART : miniUART
    port map(UART_outrdy, Clk, reset, UART_Rx, UART_Tx, RxD, TxD,
    UART_TBufE, UART_TDone, UART_DataIn, UART_DataOut);

    U_AES : aes128_fast
    port map(En_Encryp, reset, AES_start, AES_mode, load, AES_key,
    AES_data, AES_DataOut, AES_Outrdy);


    FSM : process(clk, reset, UART_DataIn, UART_DataOut, UART_Outrdy,
    UART_TbufE, UART_TDone,
    state, sub_state, AES_key, AES_Data, AES_Outrdy,
    AES_DataOut)

    -- Status message variables, with "#" as end-of-line character.

    begin

    if reset = '1' then
    state <= X"0";--state
    sub_state <= X"0";--substate

    UART_Tx <='1';--transfer data bl = '0'
    UART_Rx <='1';--trm data bl ='0'
    UART_DataIn <= (others => '0');--clear data input uart
    AES_data <= (others => '0');
    AES_key <= (others => '0');
    AES_start <= '0';--start process encrypt/decrypt
    AES_mode <='0';--signal mode encrypt/decrypt
    done <='0';--from top entity
    load <='0';--load key and data

    elsif clk'event and clk='1' then
    AES_Start <= '0';--disable start encrypt/decrypt
    UART_Tx <='1';--signal disable transmit
    UART_Rx <='1';--signal disable receive

    case state is
    -- Standby state, wait for Start bit
    when X"0" =>--when state 0
    UART_Rx <= '0';--enable read
    if UART_Outrdy ='1' then--data ready to read
    if UART_DataOut = X"31" then--start byte=1 in Hex
    state <= state +1;
    done <='0';
    elsif UART_DataOut = X"30" then--request status
    state <= X"0";--state <= "1101"
    done <= '0';

    end if;
    end if;

    when X"1" =>--when state 1
    if UART_TBufE ='1' then--check buffer empty
    UART_DataIn <= X"31";
    UART_Tx <= '0';--enable transmit data
    state <= state +1;

    end if;

    -- Receive PlainText
    when X"2" =>
    UART_Rx <= '0';--enable receive
    load <='1';--loading data
    if (UART_Outrdy ='1')then--ready to read
    case sub_state is

    when X"0" =>--sub_state
    AES_data(127 downto 120) <= UART_DataOut;
    state <= state + 1;
    sub_state <= sub_state +1;
    when X"1" =>
    AES_data(119 downto 112) <= UART_DataOut;
    state <= state + 1;
    sub_state <= sub_state +1;
    when X"2" =>
    AES_data(111 downto 104) <= UART_DataOut;
    state <= state + 1;
    sub_state <= sub_state +1;
    when X"3" =>
    AES_data(103 downto 96) <= UART_DataOut;
    state <= state + 1;
    sub_state <= sub_state +1;
    when X"4" =>
    AES_data(95 downto 88) <= UART_DataOut;
    state <= state + 1;
    sub_state <= sub_state +1;
    when X"5" =>
    AES_data(87 downto 80) <= UART_DataOut;
    state <= state + 1;
    sub_state <= sub_state +1;
    when X"6" =>
    AES_data(79 downto 72) <= UART_DataOut;
    state <= state + 1;
    sub_state <= sub_state +1;
    when X"7" =>
    AES_data(71 downto 64) <= UART_DataOut;
    state <= state + 1;
    sub_state <= sub_state +1;
    when X"8" =>
    AES_data(63 downto 56) <= UART_DataOut;
    state <= state +1;
    sub_state <= sub_state +1;
    when X"9" =>
    AES_data(55 downto 48) <= UART_DataOut;
    state <= state +1;
    sub_state <= sub_state +1;
    when X"A" =>
    AES_data(47 downto 40) <= UART_DataOut;
    state <= state +1;
    sub_state <= sub_state +1;
    when X"B" =>
    AES_data(39 downto 32) <= UART_DataOut;
    state <= state +1;
    sub_state <= sub_state +1;
    when X"C" =>
    AES_data(31 downto 24) <= UART_DataOut;
    state <= state +1;
    sub_state <= sub_state +1;
    when X"D" =>
    AES_data(23 downto 16) <= UART_DataOut;
    state <= state +1;
    sub_state <= sub_state +1;
    when X"E" =>
    AES_data(15 downto 8) <= UART_DataOut;
    state <= state +1;
    sub_state <= sub_state +1;
    when X"F" =>
    AES_data(7 downto 0) <= UART_DataOut;
    state <= X"4";--go to state 4
    sub_state <= X"0";

    end case;
    end if;
    --get the next byte of data
    when X"3" =>
    if UART_TBufE ='1' then--if trnsmit buffer empty
    UART_Tx <='0';--enable transmit
    UART_DataIn <= UART_DataOut;
    state <= X"2";
    end if;

    when X"4" =>
    if UART_TBufE ='1' then
    UART_Tx <='0';
    UART_DataIn <= UART_DataOut;
    state <= state +1;
    end if;

    -- Receive Encrypt or Decrypt select code
    when X"5" =>
    UART_Rx <= '0';
    if UART_Outrdy ='1' then
    if UART_Dataout = X"31" then
    AES_mode <='1';--encrypt
    elsif UART_Dataout = X"32" then
    AES_mode <='0';--decrypt

    end if;
    state <= state +1;
    end if;

    when X"6" =>--transmit mode aes
    if UART_TBufE ='1' then
    UART_Tx <='0';
    UART_DataIn <= UART_DataOut;
    state <= state +1;

    end if;

    -- Receive Cipher Key
    when X"7" =>
    UART_Rx <='0';
    load <='1';
    if (UART_Outrdy ='1') then

    case sub_state is

    when X"0" =>--sub_state
    AES_key(127 downto 120) <= UART_DataOut;
    state <= state + 1;
    sub_state <= sub_state +1;
    when X"1" =>
    AES_key(119 downto 112) <= UART_DataOut;
    state <= state + 1;
    sub_state <= sub_state +1;
    when X"2" =>
    AES_key(111 downto 104) <= UART_DataOut;
    state <= state + 1;
    sub_state <= sub_state +1;
    when X"3" =>
    AES_key(103 downto 96) <= UART_DataOut;
    state <= state + 1;
    sub_state <= sub_state +1;
    when X"4" =>
    AES_key(95 downto 88) <= UART_DataOut;
    state <= state + 1;
    sub_state <= sub_state +1;
    when X"5" =>
    AES_key(87 downto 80) <= UART_DataOut;
    state <= state + 1;
    sub_state <= sub_state +1;
    when X"6" =>
    AES_key(79 downto 72) <= UART_DataOut;
    state <= state + 1;
    sub_state <= sub_state +1;
    when X"7" =>
    AES_key(71 downto 64) <= UART_DataOut;
    state <= state + 1;
    sub_state <= sub_state +1;
    when X"8" =>
    AES_key(63 downto 56) <= UART_DataOut;
    state <= state +1;
    sub_state <= sub_state +1;
    when X"9" =>
    AES_key(55 downto 48) <= UART_DataOut;
    state <= state +1;
    sub_state <= sub_state +1;
    when X"A" =>
    AES_key(47 downto 40) <= UART_DataOut;
    state <= state +1;
    sub_state <= sub_state +1;
    when X"B" =>
    AES_key(39 downto 32) <= UART_DataOut;
    state <= state +1;
    sub_state <= sub_state +1;
    when X"C" =>
    AES_key(31 downto 24) <= UART_DataOut;
    state <= state +1;
    sub_state <= sub_state +1;
    when X"D" =>
    AES_key(23 downto 16) <= UART_DataOut;
    state <= state +1;
    sub_state <= sub_state +1;
    when X"E" =>
    AES_key(15 downto 8) <= UART_DataOut;
    state <= state +1;
    sub_state <= sub_state +1;
    when X"F" =>
    AES_key(7 downto 0) <= UART_DataOut;
    state <= X"9";--go to state 9
    sub_state <= X"0";
    end case;

    end if;

    --get the next byte of key
    when X"8" =>
    if UART_TBufE ='1' then
    UART_Tx <='0';
    UART_DataIn <= UART_DataOut;
    state <= X"7";
    end if;

    when X"9" =>--state 9
    if UART_TBufE ='1' then--transmit buffer kosong
    UART_Tx <='0';--enable transmit
    UART_DataIn <= UART_DataOut;
    AES_start <='1';--start encrypt/decrypt
    state <= state +1;
    end if;

    -- Cipher done, transmit CipherText out
    when X"A" =>--state 10

    if (UART_TBufE ='1' and AES_Outrdy='1') then-- aes_outready
    UART_Tx <='0';
    case sub_state is
    when X"0" =>
    UART_DataIn <= AES_DataOut(127 downto 120);
    sub_state <= sub_state +1;
    state <= state +1;
    when X"1" =>
    UART_DataIn <= AES_DataOut(119 downto 112);
    sub_state <= sub_state +1;
    state <= state +1;
    when X"2" =>
    UART_DataIn <= AES_DataOut(111 downto 104);
    sub_state <= sub_state +1;
    state <= state +1;
    when X"3" =>
    UART_DataIn <= AES_DataOut(103 downto 96);
    sub_state <= sub_state +1;
    state <= state +1;
    when X"4" =>
    UART_DataIn <= AES_DataOut(95 downto 88);
    sub_state <= sub_state +1;
    state <= state +1;
    when X"5" =>
    UART_DataIn <= AES_DataOut(87 downto 80);
    sub_state <= sub_state +1;
    state <= state +1;
    when X"6" =>
    UART_DataIn <= AES_DataOut(79 downto 72);
    sub_state <= sub_state +1;
    state <= state +1;
    when X"7" =>
    UART_DataIn <= AES_DataOut(71 downto 64);
    sub_state <= sub_state +1;
    state <= state +1;
    when X"8" =>
    UART_DataIn <= AES_DataOut(63 downto 56);
    sub_state <= sub_state +1;
    state <= state +1;
    when X"9" =>
    UART_DataIn <= AES_DataOut(55 downto 48);
    sub_state <= sub_state +1;
    state <= state +1;
    when X"A" =>
    UART_DataIn <= AES_DataOut(47 downto 40);
    sub_state <= sub_state +1;
    state <= state +1;
    when X"B" =>
    UART_DataIn <= AES_DataOut(39 downto 32);
    sub_state <= sub_state +1;
    state <= state +1;
    when X"C" =>
    UART_DataIn <= AES_DataOut(31 downto 24);
    sub_state <= sub_state +1;
    state <= state +1;
    when X"D" =>
    UART_DataIn <= AES_DataOut(23 downto 16);
    sub_state <= sub_state +1;
    state <= state +1;
    when X"E" =>
    UART_DataIn <= AES_DataOut(15 downto 8);
    sub_state <= sub_state +1;
    state <= state +1;
    when X"F" =>
    UART_DataIn <= AES_DataOut(7 downto 0);
    state <= X"C";
    sub_state <= X"0";

    end case;

    end if;

    when X"B" =>--state11
    if UART_TbufE ='0' then--transmit not ready
    state <= X"A";-- repeat transmit
    end if;

    when X"C" =>--
    state <= X"0"; -- repeat
    done <='1';--complete transmit


    when others => null;
    end case;
    end if;
    end process FSM;


    end final_aes128_arch;

    this is my top entity program...

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  2. #2
    Full Member level 2
    Points: 2,474, Level: 11

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    Re: need advice and help!!!

    first of all you must do identination to your code.

    second of all you only need to put clk, reset in the sensitivity list of the fsm.



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  3. #3
    Newbie level 2
    Points: 1,213, Level: 7

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    Re: need advice and help!!!

    thanx for reply!!
    so you mean that i need to put clk and reset only into a fsm state that sensitive to both of it...i will try...



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