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How to write a logic in Verilog for creating a latch?

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r_p_sanna

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Hi,
if i have to write a logic for creating a latch in verilog, how do i do it ?
 

latch verilog

Its very simple ...
here it goes
Code: 
module latch(
   // Outputs
   dout,
   // Inputs
   din, le
   );
   input din;
   output dout;
   input  le; // latch enable
   reg dout;
   always @(din or le)
     if (le == 1'b1)
       dout = din;
   
endmodule // latch
 

latch in verilog

thanks. i was thinking in lines of, if i don't create the default in case statement, latch is inferred. is there any other way that a latch can be inferred ?
 

verilog inferred latch

in three case:
1. if no else
2. sensitive list is not complete
3. case condition is not full
 

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    r_p_sanna

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latch verilog code

instead of using
always @(posedge clk)

try using
always @(enable)

:)
a latch is trigger by signal other than clock :)
 

verilog latch model

hi,
sensitive list not complete can not produce latch, when simulating , it behaves just like latch, but after synthesize, it is still combinational logic. it's a differece between simulation and synthesize.
 

verilog latch code

yes , only if and case can produce latch
 

latch code verilog

One of the best way to ensure that latches are not inferred is to check all that all the variables being computed in the given block are evaluated in very possible way
 

Re: latch in verilog

nand_gates' original code should be modified to -

Code: 
module latch( 
   // Outputs 
   dout, 
   // Inputs 
   din, le 
   ); 
   input din; 
   output dout; 
   input  le; // latch enable 
   reg dout; 
   always @(din or le) 
     if (le == 1'b1) 
       dout <= din;   //Use non-blocking
    
endmodule // latch

Reference:
From Cliff Cummings' "Nonblocking Assignments in Verilog Synthesis, Coding
Styles That Kill!" -

Pg. 5 -
"Guideline #2: When modeling latches, use nonblocking assignments."
 

always statement without the "@" symbol is an inferred latch..
 

module dlatch_reset (
data ,
en ,
reset ,
q
);

input data, en, reset ;


output q;


reg q;

always @ ( en or reset or data)
if (~reset) begin
q <= 1'b0;
end else if (en) begin
q <= data;
end

endmodule
 

Re: verilog latch model

IF i don't mention any edge triggered clock in always i.e. always @ (* or x or y or z or ..... ) , then this would produce latch . Specifying "always @ (posedge clk or negedge clk or .... )" won't produce latch.You need to mention this in always , otherwise it is taken as level sensitive n would produce a latch.
linuxluo said:
hi,
sensitive list not complete can not produce latch, when simulating , it behaves just like latch, but after synthesize, it is still combinational logic. it's a differece between simulation and synthesize.
Click to expand...
 

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