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Increasing or reducing the total number of clock cycles ?

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elecs_gene

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basic doubt!!

hi guys,
i have a fundamental doubt..i have a circuit which has some combinational elements and to reduce my critical path,i introduce a flip-flop at each intermediate stage so that the clock frequency of operation enormously shoots up..but,at the same time,if i increase the number of flip-flops,then the total number of clock cycles required to complete an operation increases enormously..now,my question is which to choose??whether,i should pipeline at each stage so as to increase the clock frequency,there by increasing my number of clock cycles or should i have restricted flips to reduce the total number of clock cycles??which would give u a better performance in general..

regards
 

basic doubt!!

pipelined with higher freq is better for throuput.
consider a big only combinational circuit .. say its takes 100ns to perform a calculation.
if you pipline it with 100 stages uniformly.. clock is now 1ns..
you will get 1 output every 1ns... while in combi circuit you will get 1 output every 100ns
 

basic doubt!!

i think the time it takes for the data to travel between registers is considerably less than when it is totally combinational block. thats the reason why we pipeline it using flops
 

basic doubt!!

I think pipeline method is better if the critical path delay is more.
since the complete operation time before and after the pipeline is almost same.
so u r increasing the clk freq which is advantage for other operations. ofcourse it takes more clock cycles to complete the operation.
 

Re: basic doubt!!

thanks for ur thoughts guys...so,i agree the increase in timing is a good gain...but,consider about the power?if number of flops is increased,then for the sake of timing,you are drastically increasing the switching power,the clock has to be routed to all those flops,increasing the net length and so on...now, for a optimum design which is the methodology am i supposed to adopt--comprisize on area or power?

regards
 

basic doubt!!

clock is not the only thing that consumes power.. Glitches in combinational ciruits are also power consuming.... but i think more important factor is througput.. if ur thruput requirement is less , there is no harm in building large combi ckts.
 

Re: basic doubt!!

in circuit design, there is 3 areas to consider:
timing, area & power

most of the time we focus on timing more than the remaining 2, unless u want to design portable device like mobile phone or ipod
 

Re: basic doubt!!

by puting flip flops by breaking long combinational ckts, will increase throughput at a higher frequency of operation. only problem is that it adds some extra latency
 

basic doubt!!

pipeline definitely will help.more throughput at the expense of latency.
but thats how robust design need to be designed.
 

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