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State machine which changes its state on both clock edges

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pankaj

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Both clock edges

Hello,
Is it possible to design a state machine in VHDL or Verilog which changes its state on both the edges of the clock.

Pankaj
 

Re: Both clock edges

I have never seen a construct that would allow you to do this. In my opinion, you need to run the clock through a DLL or DCM to increase the frequency by 2X. Then use this higher speed clock to run the state machine. The effect would be the same as running on both edges.
However, before making any changes, I think you need to evaluate exactly why such operation is needed. Most often it is because the existing state machine is not correct to the task and the designer is looking for an easy way to shoe horn in additional features. If this is the case, let me tell you from the hard experience, you are better off just redesigning the state machine now. Every time I tried to hot patch it has ultimately failed.

---- Steve
 

Both clock edges

I agree with banjo.

it's a good way for your Design.
 

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