same problem ....xilinx failed to open library SIMPRIM..

library simprim not found

Hi Friends ,
I tried to simulate Post -place and Route Model from Xilinx ise 7.1 but intially i got error vcom failed ,i went thro the messages and found i need to create a VLIB SIMPRIM and then i need to go to xilinx/vhdl/src/simprims.. and select all vhd file and compile it .
i repeated this 3 times and then i tried to runthe simulation again .but i have been getting folllowing errrors..



do testbench.tdo
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim SE vcom 6.1d Compiler 2006.01 Jan 23 2006
# -- Loading package standard
# -- Loading package std_logic_1164
# ** Error: (vcom-11) Could not find simprim.vcomponents.
# ** Error: ford_timesim.vhd(38): (vcom-1195) Cannot find expanded name: 'simprim.vcomponents'.
# ** Error: ford_timesim.vhd(38): Unknown record element "vcomponents".
# ** Error: (vcom-11) Could not find simprim.vpackage.
# ** Error: ford_timesim.vhd(39): (vcom-1195) Cannot find expanded name: 'simprim.vpackage'.
# ** Error: ford_timesim.vhd(39): Unknown record element "vpackage".
# ** Error: ford_timesim.vhd(41): VHDL Compiler exiting
# ** Error: C:/Modeltech_eval_6.1d/win32/vcom failed.
# Error in macro ./testbench.tdo line 6
# C:/Modeltech_eval_6.1d/win32/vcom failed.
# while executing
# "vcom -87 -explicit ford_timesim.vhd"



Reply soon
Thanks
Harsh

library simprim not found.

try to compile again make sure mapped the libraries correctly and put the include libraraies und use libraray.all in vhdl.

simprim library

U have to compile ur simprim library that is available in ur xilinx directory in the VHDL folder (src) .since ur using modelsim SE u need to compile them in ur modelsim only.Once U r compiling is over u add it as library in ur project.(u need to map it).If u have any problems let me know I worked on it.

library simprim

hi,

I believe most of us faced this prob before. Below is Xilinx website. U can check it out...personally, it is very useful and helpful. Thanx echo47 .

**broken link removed**

Hope it helps,
no_mad

simprim ise 11

while compiling simprims for VHDL, compilation of the three libraries has to be done in s specific sequence.


vlib $VHDL_DESTN/simprim
vmap simprim $VHDL_DESTN/simprim
vcom -87 -work simprim $XILINX/vhdl/src/simprims/simprim_Vpackage.vhd
vcom -87 -work simprim $XILINX/vhdl/src/simprims/simprim_Vcomponents.vhd
vcom -87 -work simprim $XILINX/vhdl/src/simprims/simprim_VITAL.vhd

check this...
**broken link removed**

What the hell, can't I simulate post-PAR model with Isim?..

Sure you can. I've been doing far too much post place & route simulation lately. And in Isim (13.1) no less. So what makes you think you can't?

mrflibble said:

Sure you can. I've been doing far too much post place & route simulation lately. And in Isim (13.1) no less. So what makes you think you can't?

Click to expand...

As far as I understand, in order to simulate post-PAR model, I should compile SIMPRIM library. And to do that, I should choose the simulator I'll be using. And Isim is not in the list.
Sorry for the stupid question, It's the first time I'm trying to simulate post-PAR model. I was able to simulate in Isim without compiling SIMPRIM (by manually creating library SIMPRIM in the project and adding proper vhd files), but it looked as though the model wasn't actually simulated: I only got U's and X's on outputs, and it was simulating too fast. I just don't undersatnd how to do it...

When I used Modelsim with ISE I always had to run compxlib to create the simulation libraries. But when using Isim this isn't needed (AFAIK). Plus, when it doesn't know the simulation model you would get a whole bunch of errors. So judging by the fact that you get a running simulation I'd say you have the libraries alright.

Getting X's and such during post PAR simulation sounds like:
1 - you forgot to initialize some registers, or
2 - your favorite latches or other asynchronous logic result in setup/hold time violations.

Initialization is easy enough to check and fix. As for async registers/latches, to get some meaningful simulation results you might want to set the ASYNC_REG attribute. So something like:


And as always, you may want to RTFM to see what ASYNC_REG does... I always use it on the meta-stable register of a synchronizer, things like that...

Hope that helps.

mrflibble said:

So judging by the fact that you get a running simulation I'd say you have the libraries alright.

Click to expand...

My thoughts exactly.
I have no latches in the design, not anymore.
And I didn't forget to initialize registers, since everything is initialized upon reset and I did issue reset signal. And then again, it was simulating way too fast. Like 5 times faster than corresponding RTL model does.

And then again, it was simulating way too fast. Like 5 times faster than corresponding RTL model does.

Click to expand...

Not quite sure what you mean by that.

I meant the time it took to simulate certain amount of model time was very much less, than time it took to simulate the source VHDL model for the same amount of model time.
P.S. Sorry for my English.

---------- Post added at 14:49 ---------- Previous post was at 14:46 ----------

I was able to get post-PAR model simulated in Isim at the university (in ISE 10.1). By the way, the simulation went very slowly (as it should). However, at home I still wasn't able to succefully simulate. Neither in ISE 12.3, nor in 13.1.
In ISE 10.1 the source files for SIMPRIM library are not the same as in 12.3/13.1. I mean the amount of files and their structure. In 12.3 there are no sources for IEEE.Vital library (I beleive it is shipped precompiled), while in 10.1 there is a source code for that lib.

I really would expect the simprim stuff for vital to be included as well in ISE 12.3/13.1. Are you sure it is not something like SIM_MODE = FAST vs SAFE setting that is different. Besides xilinx has this amusing habit of changing tool default settings every now and then. So you may want to check the simulation options/flags for the two different environments (home vs uni).

One last thing that I remembered when I was trying to think of "what does he mean with simulation running faster" ... when you want to look at the low-level timing stuff (due to routing delays, etc) then you may want to set the simulation timescale to 1ps/1ps. That also makes a difference in the simulation results for post PAR.

OK, I got it.
It is only now that I have noticed a warning (well, a hundred of warnings):
" <x_xor2> remains a black-box since it has no binding entity.". And similar for other components.
And I think I've found source files for all the primitives.
One thing I really hate about ISE - it's really bad at handling librarys with large amount of files...

By "simulation running too fast" I meant exactly what I said

Click to expand...

yes, I got what you meant the last time. Just not before that. And during that "before that" time I had this background process finding possible matches for me for "what the hell does he mean". And one of them that came up was the timescale thing. But I understand what you mean now. Shorter simulation runtime by a factor of 5, for the same simulation but on 2 different environments.

Hence, see previous statement about SIM_MODE. Maybe different settings? If at home you run with SIM_MODE = FAST and at the university with SIM_MODE = SAFE, I could see how that would result in these differences...


Besides, maybe at home you have an overclocked i5-2500k while at the uni you are working on an old slowlaris box. Who knows.

Once again, sorry for not being concise.

mrflibble said:

Maybe different settings?

Click to expand...

Nope...

I've added the missing files into SIMPRIM library. 250 files sent ISE into knockdown. I'll wait, amybe it will eventually process them...

---------- Post added at 19:20 ---------- Previous post was at 19:07 ----------

Grrrrr!
Now I have no warnings while compiling and elaborating, and simulation runs slowly (just as I like:-D), but again - nothing on output ports of UUT...

Alexium said:

OK, I got it.
It is only now that I have noticed a warning (well, a hundred of warnings):
" <x_xor2> remains a black-box since it has no binding entity.". And similar for other components.
And I think I've found source files for all the primitives.
One thing I really hate about ISE - it's really bad at handling librarys with large amount of files...

Click to expand...

A-HA. Now he tells us. But glad you found that one.

You needed the ones in "ise_124/ISE_DS/ISE/vhdl/src/simprims/" or something like it?

Now I have no warnings while compiling and elaborating, and simulation runs slowly (just as I like:-D), but again - nothing on output ports of UUT...

Click to expand...

Nothing, not even a clock signal or something like that?

mrflibble said:

You needed the ones in "ise_124/ISE_DS/ISE/vhdl/src/simprims/" or something like it?

Click to expand...

Yep. I initially included some, but not all (really don't understand how could it happen).

mrflibble said:

Nothing, not even a clock signal or something like that?

Click to expand...

Clock signal (and some other signals) is generated by testbench, it's simple plain VHDL. It's UUT is post-PAR model, to which testbench feeds input signals (clock included). And outputs of UUT are U's.

Alexium said:

Yep. I initially included some, but not all (really don't understand how could it happen).


Clock signal (and some other signals) is generated by testbench, it's simple plain VHDL. It's UUT is post-PAR model, to which testbench feeds input signals (clock included). And outputs of UUT are U's.

Click to expand...

Understood. What I mean is ... you generate the clock in the testbench. And it is intended to be an input to the UUT, right? What I mean is when you view the waveform of the clock IN the UUT (as opposed to the toplevel testbench), do you also see the clock (and presumably reset) signal? Sort of as a sanity check for connections that did not go as intended. Another favorite of mine is to connect the wrong width bus. It won't complain, will simulate, and will give you a whole lot of X's or Z's...

That's what I meant by "now even clock?" since I would expect at least something like that to arrive in one piece to the UUT module...

mrflibble said:

That's what I meant by "now even clock?" since I would expect at least something like that to arrive in one piece to the UUT module...

Click to expand...

I'm really stupid today. Now I got it, thanks for the idea.
Inside UUT are signals, and great many of them. Many of them are switching, much more are not (but initialized). U's are very few.
Actually, my UUT has only one significant output (serial output), and it's constantly '1' (which is idle state). And another output is U, though it should have been set to 0 by reset.
Weird, considering the project works in hardware.

---------- Post added at 23:08 ---------- Previous post was at 22:54 ----------

Tried both in 12.3 and 13.1 - all the same.
Seems like I'll have to download and install 10.1, but it's so old, Isim got much better since then...