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Pmos is twice of NMOS

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p_shinde

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why pmos speed is slower than that of nmos

hi,

PMOS lenght is twice that of NMOS, as mobility of electrons is twice that of hole and to make fall and rise time equal.

Can anyone please explain this with an example, its urgent.

thanks in advance.
Prasad
 

Hi Prasad!

The drain current of a mosfet is proportional to mobility and the ratio w/l.
Electron mobility is typically 3-4 times that of a hole.
So to have comparable drive power, the sizing (in an inverter) is done such that the lengths are the same, but the width of PMOS is 3-4 times that of NMOS.

Hope it is clear now.

Giri
 

yes, PMOS width is generally twice of NMOS,

because NMOS's carrier is electron and PMOS's

carrier is hole. the mobility of electron is much faster

than hole. doing so is to get approximately equal fall and

rise time.

best regards




p_shinde said:
hi,

PMOS lenght is twice that of NMOS, as mobility of electrons is twice that of hole and to make fall and rise time equal.

Can anyone please explain this with an example, its urgent.

thanks in advance.
Prasad
Click to expand...
 

I think Giri has explained it quite rightly. The width of PMOS is almost 3 times that of NMOS to get comparative rise and fall times and switching of operation.

To give you an example.Traditionally nandgates are used as the basic desing gates(Universal Gate) compared to norgates(also universal gates).
Can you think of the reason behind this??

The reason is that if you construct these gates in CMOS you will observe that for Nand gates the PMOS are in parallel while for NOR the PMOS gates are in series. Now since the mobility is higer in NMOS we prefer parallel PMOS of Nand gates rather than series PMOS of Nor.
 

Usually to make the rise and fall times equal and also to get equal drive strength from both the PMOS and NMOS we make the width of the PMOS either 2 or 3 times wider. For example if the NMOS width is 3um the PMOS is made 6um-9um wider.

We also need to do beta matching to get equal drive strengths from PMOS and NMOS. Ideally we want the switching threshold point in the Voltage Transfer Characteristic curve to be at VDD/2. So doing a beta matching would help to achieve a switching threshold value close to VDD/2.
 

In other way,
rise and fall time of an inverter depends on the charging and discharging of the o/p capacitor.
so to get equal rise n fall time we require to made charging and discharging currents equal ...
so the charging current depends on the mobility and w/l of the PMOS so we require to make larger PMOS when compare to the NMOS
 

PMOS is slower than NMOS of same size . So, if u want to have both of same speed, you need to size the pmos higher(maybe roughly 3 times). Also, The mobility of holes is greater than the electrons by approximately 2 to 3 times.

Hence the equation Wp = 2 to 3 times Wn. So, is the size of P-MOSFET greater than the N-MOSFET

Havefun,
ALI
 

yes, in order to compensate for the different mobilities of nmos and pmos (un>up)....the width of pmos is chosen larger than that of nmos..this is to have the same current in both

also, nand gates are more used in digital design since the pmos used is in parallel while in the nor gates the pmos is in series....which means that in nand gates u don't need to scale the pmos used to match the nmos...while in nor gates, there should be some scaling for the pmos cause it is used in series....so nand gates use less area
 

In terms of space, PMOS is twice of NMOS.

Interms of mobility and speed (timing), NMOS is twice of PMOS
 

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