sixth
Member level 4
As all know, clock jitter has important effect to the sampling system and can decrease the sytem performance greatly. But is there a limit about the performance descend?
For the sample and hod circuit, the SNR due to clock jitter can be expressed as SNR=-20*log(2*pi*Fin*deltat),where deltat is the variation of the clock jitter. I dont know if the the deltat is cycle-to-cycle jitter or a T-cycle jitter(accumulated jitter). For a PLL or a crystal, the cycle-to-cycle jitter will be accumulated without a limit. Then it seems we can draw a conclusion that the system performance will inevitably decrease to zero due to the accumulated jitter. Is this right?
sixth
For the sample and hod circuit, the SNR due to clock jitter can be expressed as SNR=-20*log(2*pi*Fin*deltat),where deltat is the variation of the clock jitter. I dont know if the the deltat is cycle-to-cycle jitter or a T-cycle jitter(accumulated jitter). For a PLL or a crystal, the cycle-to-cycle jitter will be accumulated without a limit. Then it seems we can draw a conclusion that the system performance will inevitably decrease to zero due to the accumulated jitter. Is this right?
sixth