Below MIM Cap cannot have MOS, metal and etc?

Any ideal that below MIM Cap (using M5 and a metal layer between M5 and M6), it cannot have MOS, metal and etc?

Is it due to parasitic C of bottom plate or process reason?

Thanks.

I think it is mainly because of processing issue. While parasitics increasing can be avoided. This rule maybe not a fatal rule for I know some product put devices under MIM caps for die size issue. You can consult your foundry.

It's the process problem. The distance of MIM is very short. some one on below it will be effect the distance

Mainly it's due to the parasitic capacitance problem....where if it's not neglected then will accour device problem

To my experience with generations about 0.25um & 0.18um fab,
It is not process issue;
See under modern CMP (chemical mechanical polish) technology,
they fine polish after each inter-metal oxide layers.
And MiM cap resides below last metal (top floor), which is more than 4um
away from silicon surface. And after more than 4 times of CMP, it's real flat up there.
Plus the thickness of the MiM dielectric ayer is fabricated by chemical deposition,
the control factor is time (~10sec).
I don't think a 4um away 0.1um~0.2um thick poly gate can affect it's capacitance after 4 CMP.
The real problem here is about modeling ( or parasitic couling...) or simulation,
foundry do not believe they can properly model what is really happening electrically,
and then presim and postsim could fail.
Integrated circuit business is such a big business,
that they should rule out any possible risk as much as they can...

The planarisation is not perfect. Because of the metal grain structure the yield is better if there is a flat area below MIM caps. There should be therefore good reasons to take a less yield approch. One example is to combine poly/poly with MIM cap as stacked caps.

there are possibility that the capacitor has a mismatch issue. for example, for data converter, it needs very high precision cap (0.001% mismatch) which is quite difficult to get if there are other device or routing below it. routing beside it is better but keep the distance.

Certainly any underlying topography will affect the local
dielectric thickness and capacitor match, possibly reliability.

In my experience though, the rule stems more from the situation
that since these effects were anticipated, the foundry
decided to simply not qualify or model the structure with
under-features and rule them out. This has nothing to say
about whether the structure is indeed reliable or good
enough for non-match-critical uses. They simply didn't
want the work, or the headache of explaining to every
fresh face the nuances of doing less-than-ideal things
to that element, or develop complex models for what is
likely a very variable set of effects.

I've fought this fight with my own foundry and you probably
will have no better success (and forget it, if you're just a
fabless sharecropper).