Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

SRAM design issues with the W/L ratio and weak pull-up transistor

Status
Not open for further replies.

weng

Member level 1
Joined
Jan 13, 2006
Messages
32
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Activity points
1,576
Hi,

I face some problems in designing a full CMOS SRAM cell:

1. The choose of W/L ratio
The W/L of the back-to-back inverters should be the same? I saw this in somewhere. I was confuse by that because in a latch, the forward inverter should be stronger than the feedback inverter...
The Wordline transistor should have smaller W/L compare to back-to-back inverter?
How bout the Bitline transistor?

2. Why there is a need of weak pull-up transistor?
 

Re: SRAM Design problem

Try google.com.
Type "SRAM static noise"
 

Re: SRAM Design problem

refer to digital integrated circuits by jan rabey
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top