HOW TO REDUCE AREA INSIDE THE FPGA

I wrote a program for my project.
It consumes 75% of APA075 ACTEL FPGA-75000 GATES.
How do i reduce the area by using the same programming codes?
give idea for different programming techniques.

(vhdl or verilog "program" I suppose)...i would be nice if you mention some details about it...

any way first of all try to "fix" higher level architecture, including datapath redesigning and state minimization. secondly strictly following the rtl guidelines provided with synthesis tool and vhdl/verilog textbook coding techniques and approaches: like resource shareing, instantiate macros (where possible), 1-hot encoding for state machines, pipelining, for microprocessors using microprogramming instead on hardwired control, use exotic architectures: (for signal processing) bit-serial approach (see articles http://www.fpga-guru.com/ related to bit-serial fir filter design and general mutiplier impl in fpga), distributed arithmetic.

also read the tool manuall, set the tool logic and routing params to max [in you case set them to optimize the area]

You can also look at this

**broken link removed**

It's some guy who built a processor, and had area problems. He optimized his design, saving a lot of resources, and he's commenting on how he did it.