How to solve this LVS error?

Hi Guys,

Can somebody tell me how to solve this LVS error? Following is the error listed in the LVS result file.

*/W* WARNING: NO POWER ON LAYOUT SIDE
*/W* WARNING: THEN THE POWER NODE MAY BE ASSIGNED DIFFERENT SCHEMATIC NAME.


*/W* WARNING: NO GROUND ON LAYOUT SIDE
*/W* WARNING: THEN THE GROUND NODE MAY BE ASSIGNED DIFFERENT SCHEMATIC NAME.


READING CPOINT-FILE FOR INITIAL CORRESPONDENCE POINTS

*/W*** ILLEGAL LAYOUT NODE NAME: DISCARD LINE IN CPOINT-FILE:
VCC VCC
*/W*** ILLEGAL LAYOUT NODE NAME: DISCARD LINE IN CPOINT-FILE:
GND GND
*/W*** ILLEGAL LAYOUT NODE NAME: DISCARD LINE IN CPOINT-FILE:
A A
*/W*** ILLEGAL LAYOUT NODE NAME: DISCARD LINE IN CPOINT-FILE:
B B
1 ***************************************************
********* CORRESPONDENCE NODE PAIRS ***********
***************************************************


SCHEMATICS LAYOUT PAD TYPE

***TOTAL = 0***
/*W WARNING : LIST OF SCHEMATIC PADS HAVE NO LAYOUT CORRESPONDENCE
GND! 1 G
VCC! 2 P
A 3 I
B 4 O
***TOTAL = 4***

*/W** NO LAYOUT DEVICE(S), SKIPPED NET COMPARISON OF THIS CELL




***************************************************
**/L* -- SCHEMATIC AND LAYOUT MATCH **
***************************************************

Thanks a lot
Jay

u might have given different names in layout and schematic. and u have mentioned Global in any one.

I have used the CPOINT-FILE=cp.txt,

cp.txt:
VCC vcc!
GND gnd!
A A
B B

Why the LVS result says the layout node name VCC, GND, A, B are illegal?


Best Regards
Jay

When u do LVS, the pin name of layout should be same as the pin name of schematic. For example, if power pin is named VCC in the layout, the power pin should be named VCC in the schematic. Others like so.

which tool u r using ?

I am using PDRACULA, and I only draw 2 BJT in the layout, for each pin of the schematic, I only put text in the layout, and I don't know how to put pin in the layout.

which text u r putting. M1-Text M2-Text etc. or just Text layer ? if it Text layer then change it to metal text (M1-Text etc) whichever metal u r using ? say if u have M1 as VCC and GND then put M1Txt over that area and like others.

Dear vbhupendra,
Following is some part of the input-layer in LVS command file, it is a bipolar process, layer 101 is defined in my techfile as a text layer.
NP = 1
ISO = 6
B = 7
E = 11
C = 13
TH = 15
SM = 16
M = 14 TEXT = 101 ATTACH = M
;;;;;;;;;TEXT = 101 attach= M

SUBSTRATE = BULK 256

And I have defined a single NPN as follow assuming that there is no other device, can you check it for me, NP is the N+ burried layer

CONNECT-LAYER =CNPN BNPN ENPN M
AND C BULK CONT

select e inside b enpn
select b enc e bnpn
select np enc enpn cnpn
select e outside b acont1
and acont1 cnpn bcont2

CONNECT M BNPN BY CONT
CONNECT M ENPN BY CONT
CONNECT M CNPN BY bCONT2


ELEMENT BJT[NV] ENPN CNPN BNPN ENPN
*BREAK ALVS
LVSCHK[RPCAET] RESVAL=2 CAPVAL=2 DIOAREA=1 EAPER=1



Regards
Jay

Added after 1 minutes:

***********
*********
**********
**********
***********
In the layout, I use layer 101 to label the Metal line of metal1 "M"

this lvs file u have created or it is provided by foundary ?

Hi

1.please chwch the pin types (in,out,inout) for both sch and layout.

2.onemore possibility is that some fondaries specifically need the pins in the layout to of the tyoe pn layer type.

regards

vijay

This LVS file is created myself, so can you guys modify it?