liberal
Advanced Member level 4
In phase-locked loops design,simulation and applications(Roland E.best),It is said that----the bandwidth of a PLL is often specified by the 3-dB corner frequency of closed loop.
But in PLL performance ,simulation and design(National semiconductor),It is the bandwidth is drived from open loop ||G(jWc)H||=1.
why?
But in PLL performance ,simulation and design(National semiconductor),It is the bandwidth is drived from open loop ||G(jWc)H||=1.
why?