Whats wrong with my PWM ?

library ieee;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Interface definition
entity pwm_module is
       port ( data: in STD_LOGIC_VECTOR (7 downto 0);
              clk: in STD_LOGIC;
              reset: in STD_LOGIC;
              outpwm: out STD_LOGIC
       );
end pwm_module;

architecture Behavioral of pwm_module is

signal int_reg: STD_LOGIC_VECTOR (7 downto 0);
signal counter: STD_LOGIC_VECTOR (7 downto 0);
signal tc: STD_LOGIC;
signal cnt_dir: STD_LOGIC;

begin

	--store data into register
	process(clk, int_reg, reset)
	begin
   if (reset = '1') then
		int_reg <= "00000000";
	elsif (rising_edge(clk)) then
		int_reg <= data;
	end if;
	end process;

	--8 bit up/down counter
	process(clk, counter, tc, cnt_dir)
	begin
		if (tc = '1') then
			counter <= int_reg;
		elsif (rising_edge(clk)) then
			if (tc = '0' and cnt_dir = '1' and counter < "11111111") then --if not end, count up and counter < 255
				counter <= counter + 1;
			elsif (tc = '0' and cnt_dir = '0' and counter > "00000000") then
				counter <= counter - 1;
			end if;
		end if;
	end process;

	process(tc, counter, clk, reset)
	begin
		if (reset = '1') then
			tc <= '1';
		elsif (rising_edge(clk)) then
			if ((counter = "11111111") or (counter = "00000000")) then
				tc <= '1';
			else
				tc <= '0';
			end if;
		end if;
	end process;

	--generate pwm
	process(clk, tc, reset)
	begin
		if (reset = '1') then
			cnt_dir <= '0';
		elsif	(rising_edge(tc)) then
			cnt_dir <= not(cnt_dir);
		else
			cnt_dir <= cnt_dir;
		end if;
	end process;
	
	outpwm <= cnt_dir;

end Behavioral;

vlib work
vcom *.vhd
modelsim pwm_module
  add wave *
  run 10us
  exit