what is the 0.18um means in the "taped out in .18um pro

wether the length or the width of the MOSFET is 0.18um?

Added after 33 minutes:

another question
I synthesized one of my designs,and i am trying to calculate the gate count.
The DC reported the total area of my design.
I also synthesized a NAND gate ,the reported area is 7.53.And a NOT gate,the area number is 5.02
Which number should i choose to calculate the gate number?

Thanks

Re: what is the 0.18um means in the "taped out in .18um

another question
I synthesized one of my designs,and i am trying to calculate the gate number.

Click to expand...

Hi,

Maybe this might help for gate count estimation...

Things you'll need are..
1. DC area report of the design
2. Library cell unit to gates conversion factor. (From ASIC vendor)

Normally, after synthesis, SCAN flops have not been inserted. So, if you will be inserting SCAN into your design, you'll need to factor this in. Typically, the increase is 25% of noncombinational logic.

From the synthesis area report, the two items that are important are
- Combinational Area (A)
- Noncombinational area (B)

1) Compute estimated total gate count of design with SCAN flops by multiplying 1.25 to the Noncombinational area (B).
2) Add result of 1 to combinational logic(A) to get total cell area.
3) Convert cell area to gates by dividing result of from step 2 by gate conversion factor.
4) result of 3 is gate count.

0.18um is the transistor channel length. If you visualize a transistor when it is conducting, electrons flow from source to drain in the channel created by biasing the gate. The length of this channel from source to drain is the channel length. You will often hear terms like 0.18um drawn vs 0.18um effective. This is because although you may draw 0.18um in the layout tool, the actual channel length may be different. Someone who understands device physics may be expain this better.

Yeah 0.18um is the channel length of the transistor. Process technology node also specified length instead of width. Althought you may draw 0.18um, u may not get effective 0.18um because when creating the source and drain of the transistor during diffusion, there may be a lateral diffusion effect that grow under the gate, thus the effective lenght of the transistor become shorter. These information will normally be provided by the foundry or in the model file. I think Ken Martin book on Analog Integrated Circuit Design has some brief description regarding this effect.

Re: what is the 0.18um means in the "taped out in .18um

In order to determine the average size of your design after synthesis I would suggest to do the following:

1. Get the size of all nand2 gates in your library (the easiest way is to lookup the
source code of the library you are using but your method is fine if you don't
have access to it).
2. Pick one in the middle (between the smallest and the biggest one)
3. From your synthesis report grab the "total cell area", which is the sum of
combinatorial and non-combinatorial areas.
4. Divide the total cell area by the size of the mid-sized nand2 gate.


This is not very precise but widely accepted way to quote the design size in gates in the industry.