Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Parallel Plate Capacitor

Status
Not open for further replies.
hrkhari

hrkhari

Full Member level 4
Joined
Mar 4, 2004
Messages
223
Helped
6
Reputation
12
Reaction score
3
Trophy points
1,298
Activity points
2,250
Hi Guys:

In implementing a parallel plate capacitor utilizing a MOS,with the equivalent dielectric Si02, What is the effect on the effective capacitance is one plate is longer than the other, kindly do feedback. Thanks in advance

Rgds
 

This is usally the case - top plate is gate material, and bottom plate is the mosfet tub which is always bigger than the top plate.. You can estimate it simply by using just the area of the gate region, or if you want to get fancy, you can include the fringing capacitance around the periphery of the gate region.
 

for the parallel plate capacitor
the bottom plate is larger than the top plate, such as
double-poly, poly-metal...
u can caculate the fringe capacitor from the relation file.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top