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Problem in cascading several SH stages in pipelined ADC

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moisiad

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Hi all

I have designed the sample&hold stage of a 8bit pipeline ADC, which exhibits a very good behaviour. However in the case where i cascade several stages to realise the ADC, the output of each stage is getting very bad (large spikes, no correct values in some cases).
I suppose that is due charges that passes from one stage to another, as there is no any buffer between the stages.
Have every of you noticed such a problem? Do you have something to propose?

Thanks
 

it is diffcult to say. many can cause those: such as the circuit structure, PM of opa, simulator settting and so on
 

Hi sunking

I must agree that is quite difficult to indicate what is wrong without even having seen the circuit topology.

However what it seems strange to me is that even if the OPAMP is well designed (PM=60, gain 70db, settling time=14ns) and the sample and hold circuit (from Baker - CMOS Mixed Signal Circuit design, pp.355) operates good enough when it is driving just a capacitive load (I have even managed to get the triangle Vin-Vout characteristic), when it drives a SH stage the output is distorted.

Because i have no previous experience in pipeline ADC, i would appreciate if someone have ever come up with the same kind of problem, which unfortunattely is not written in books or papers (as far as i know)

Thank you for your time
 

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