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    LNA input and output matching

    l'm design a common gate LNA using CMOS technology. The input and output port of the CG-LNA need match to 50 ohm.

    i chose the W/L of the mosfet so that its 1/gm = 50 ohm = input impedence. But the problem is when i try to match the output port of the LNA to 50ohm using LC matching circuit, i found that the impedence of the input port will vary from 50ohm.
    How can i solve this problem? Why i read from the paper, they use 1/gm=50,they still can match the output port to 50ohm?

    thanks.

    regards,
    chunlee

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    LNA input and output matching

    It is due to the isolation between source and drain, if the isoation is poor the output matching will affect input matching. Also need to make sure the output L network does not change your DC bias of your active device, sometimes people use wrong L network and directly connect the source or drain to ground through inductor. Instead of common gate LNA, common source casecode with common gate is better for RF application.



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    Re: LNA input and output matching

    thanks for pi331133.

    i'm design common gate LNA. As i know, the Cgd will resonance with inductor at the output port at the desired freq. Is it Cgd still will degrade the circuit isolation? how can improve the LNA isolation for common gate?

    thanks again...



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    LNA input and output matching

    I think cascode configuration is better.



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    Re: LNA input and output matching

    i think that the input match only for the lowest noise.
    the output match is for the maxgain .



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    LNA input and output matching

    Hi Chunlee, I think for common gate LNA, the gate is a good AC ground, so in theory, Cgd is no effect on input. I think since you match input to 50 Ohm, your Gm is about 20 mS. Draw the small signal circuit of common gate LNA, the drain voltage affect the ids, ids affect Vgs. You can perform a s-parameter simulation, to get the S12 and S21, then you will know the Gain of LNA and the isolation of drain and source. For your design, is it a board level design or a IC level design, if it is a IC level design, I highly recommond the common source LNA. For common Gate LNA, the isolaton betwen source and drain within one transistor is poor. For common source LNA in order to minimize the Cgd effect of the common source transistor, a casecode common gate transistor is inserted, even so, the output still has effect on input matching. somepapers focus on insert some LC network between common source transistor and common gate transistor to perform better matching of these two stages for a minimum overall NF.

    In fact the matching is not important for LNA, if you can achieve a matching better than -20 dB, that is enough. The key specs for LNA are the power, IP3, Power Gain and NF. unless you are designing a standalone LNA IC, the output matching no need to matching to 50 Ohm, it should be matched to the input of mixer or buffer. The trade-off between power and NF is still a problem of LNA. For LNA the goal is how to achieve the best NF under the limited power and ESD condition. For the specs of gain, IP3, etc they are not so hard to achieve. Thomas H Lee has a paper focuses on LNA design, he discusses the different structures of LNAs and their related minimum NF in detail. It is a very good paper for LNA design. You may have a look of it.



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    Re: LNA input and output matching

    hi, pi331133. thank you for your reply.

    i have one more question.

    most of the CMOS LNA papers state their LNA gain as s21. but to determine s21, we need to specify the source and load impedence. usually we use 50ohm for our source impedence. But what is the value of load impedence normally they use to determine s-parameter? is it 50ohm?



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    Re: LNA input and output matching

    Hi Chunlee,

    The gain is S21 or S12, it is depend on which terminal is input (it is not a problem, am I right? ) . For the power gain, as we know, power=sqr(voltage)/impedance. So you can refer to this to calculate the power gain for different output impedance. During simulation, if your simulator can let you select the matching impedance at the output (e.g. ADS), that will be easy for you. If not, you need to calculate it by yourself. (According to the equation mentioned above). Let's assume, at the input there are , Vin, Rin and Pin, the out are Vout, Rout and Pout. So the power gain is Pout/Pin=(Vout/Vin)^2*(Rin/Rout). Normally the Rin=Rout=50, so the power gain is same as voltage gain, if Rin≠Rout, you need to care about the impedance ratio.

    In s-parameter, the 50 Ohm is a widely used normalized value for simulation, you can specify different value, once you do this, you should keep in mind that your simulation is not refer to 50 Ohm. you may need handy calculate some results. If your simulator is good enough, it may convert it for you automatically, you can refer to the manual of your simulator to have an idea.

    For the load impedance, it depend on the what circuit followed your LNA. Is it a filter or mixer or buffer. e.g. if the circuit is a mixer, you may specify hundreds Ohm or 1K for the load. I think you can just specify a value to have a try. Thank you.



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    Re: LNA input and output matching

    hi pi331133, thank you for your reply. i really appreciate it. i just start my research in CMOS RFIC a few months ago. i have many things want to learn,especially for rf circuit design.

    do u know how to use hspice? i use hsipe for my RF circuit simulation.

    thank you again.



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    LNA input and output matching

    Hi Chunlee, Welcome to RFIC field. This forum is a very good forum. I leraned much from it. Also we can help each other from this forum. For hspice, I am not skilled in it. The manual is always the best teacher for EDA tools. However, if have problem in the design, it is aleays my pleasure to share the problem from you.



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    LNA input and output matching

    for common source lna whats the typical value for S12 cause i have desined an uwb lna and I am getting S12 less than -20 dB, S22 less then -10 dB but S11 less than -3 dB which means I am not getting good input match ... any help !!

    /k



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    Re: LNA input and output matching

    Hi pi331133
    as you referred above, some paper focus on intermatching between common source and common gate using LC network. Really it can improve overall NF, but it deteriorate the input matching(S11), do you think this method is usefull in practice??



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