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which is better to use : Registers or RAM ?

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omara007

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Hi guys ..
I have a design that requires 2 KByte of storage .. with each element of storage equal to 2 bytes and a number of elements equal to 1024.
Which is better, to implement this storage as registers or RAM ?
Regards
 

Logically analysing your requirement itself, for 2k storage you will need 2k registers which far far times larger than the 2k RAM. RAMs have been designed only for reducing our usual space occupied by registers. Unless your memory requirement is not of standard sizes, we use only RAMs.
 

If my main concern is power consumption , what do you think ? .. Registers or RAM ? ..
 

If power consumption is ur idea, Then obviously RAMs are the better choice. Because they come as macros which are optimised for power for the vendor.
Also..Smaller memories are faster and consume less dynamic power and so you can build larger memories with them.

But if we use flops then we have to depend on the tool to optimise the block for area and power which I am very much sure will be less efficient than the Memory macro vendors.
 

so , what's the best RAM chose for a total memory of 2KB and a requirement of low-power consumption ?
 

omara007 said:
so , what's the best RAM chose for a total memory of 2KB and a requirement of low-power consumption ?

If you are too consious about power I would suggest 1-T SRAM rather than 6-T SRAM. well I think you should consider the fact that using a RAM increases the testing circuitry(memory bist) and a memory controller... Also testability of the circuit reduces.

Check out Register files(usually used for mid-size memories) from your foundry.
They can be tested with scan chains and more easy to use.




Added after 3 minutes:

dynamicdude said:
2KB ram is the doubtless choice..

??????
 

RAM is better solution for power consumption.
 

In fact, the register and RAM is same. Library vendor just design them by different concern.
Generally, the register is smaller than RAM, and the power is more less than RAM.
 

Yun Lin said:
In fact, the register and RAM is same. Library vendor just design them by different concern.
Generally, the register is smaller than RAM, and the power is more less than RAM.

Now there is a conflect !! .. which is smaller and less power consuming ???? Some of you said RAM in the beginning and some others said Registers !!
 

register array is faster , but bigger area , consume more power;
ram is lower,but more compact,less power consumed.
 

archillios said:
register array is faster , but bigger area , consume more power;
ram is lower,but more compact,less power consumed.

what about the cost ? .. RAM or Register Array is of a higher cost ?
 

RAM is definatly a better choise. Not sure weather you are using ASIC or FPGA.
In FPGA's you can get some RAM modules optimized for power.
IN ASIC RAM definatly comes with testing logic overhead
 

sameer_dlh25 said:
IN ASIC RAM definatly comes with testing logic overhead

Yes I am talking about ASIC .. but do you mean by (testing logic overhead ) ? .. do u mean (bist) ?
 

Yun Lin said:
In fact, the register and RAM is same. Library vendor just design them by different concern.
Generally, the register is smaller than RAM, and the power is more less than RAM.

As i know, the RAM is fabricated with quite different technology compared with registers provided by the library vendor so as to reduce the area, in other words, to increase the density. I've never read such article or guides that a similar RAM unit has the similar area compared with the register to realize the same function.

In addition, their structures are also obviously different: the RAM normally costs 6-MOS which are much less than the required cells of the registers to constitute a memory. Of course, here the assumption that the memory is pretty large since some additional circuits are necessary to realize the functionality of reading or writing and amplifying the signals and so on.

From the perspective of power consumption, since the register will require a clock per each which will doubtless consume much more power than the RAM structure since it only samples the address. And the data triggering is very similar and the overhead power dissipation consumed by the additional circuits aforementioned is very small if the space is pretty large.


Of course, if the memory is not very large, then the designer shall trade off these metrics carefully and better to refer to some other's data sheet.
 

The memory complier I used has already provide the RAM and register file(not synthesised by synthesizer).
When the memory size is small than 1024x16, the area of register file is small than that of RAM and the peak or average power of regfile is also small than RAM from its report.

PS: the case I try is T-like 0.18 process.

Sincerely,
Jarod
 

jarodz said:
The memory complier I used has already provide the RAM and register file(not synthesised by synthesizer).
When the memory size is small than 1024x16, the area of register file is small than that of RAM and the peak or average power of regfile is also small than RAM from its report.

PS: the case I try is T-like 0.18 process.

Sincerely,
Jarod

Hi,jardoz
Can you provide us with some good data concerning the power consumption and area cost? If some chart can be provided, then it's much better!

Thanks a lot!:D
 

jarodz said:
The memory complier I used has already provide the RAM and register file(not synthesised by synthesizer).
When the memory size is small than 1024x16, the area of register file is small than that of RAM and the peak or average power of regfile is also small than RAM from its report.

PS: the case I try is T-like 0.18 process.

Sincerely,
Jarod


These are some helpful information .. numbers give clearer view to the solution of the problem .. Yet, what's the difference between the registers I do design in my RTL (and the backend team puts them close together in the layout) and the register file supplied by the foundry ?
 

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