Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

[Help]Verilog Problem?

Status
Not open for further replies.

billjoy

Member level 1
Joined
Apr 19, 2005
Messages
33
Helped
1
Reputation
2
Reaction score
0
Trophy points
1,286
Activity points
1,569
error [ibc] invalid bounds count + vcs error

use VCS compiler
I need a two dimension array
but VCS can not accept this syntax
EX :
......
....
for(i=0;i<RANGE; i=i+1)
data={chip.mem[127:63],chips.mem[127:63]}
.....

it seems VCS cannot accept a variable i ,
so
Q: How to solve this problem?
 

v2ks, verilog

Can you show us a little more code? Maybe a small complete module.
 

vcs invalid bounds count

it's a simulation model,
two dimension array can let simulate more convinence

it's inside a task :
//===========

reg [32:0]mem[127:0];
reg [127:0]databuf;

task a;
input
output
int i;
begin i=0
@(.....)
repeat(33) begin
databuf={chip.mem[127:63],chips.mem[127:63]} ;
$display("...%h..............".databuf);
.........
end
i=i+1;
...
end
endtask

//===========use VCS
 

Can you post the ERROR that VCS generates for this part of code???
 

here is the error message
without +v2k argument
//=================

Error-[V2KS] Verilog 2000 IEEE 1364-2000 syntax used. Please compile with +v2k
to support this construct
multidimensional select.
"./model/aa.inc", 11



//=================
with +v2k argument

Error-[IBC] Invalid bounds count
The following access has an invalid number of indices.
"./model/aa.inc", 11:
pattern.chip.mem[127][63]

1error

By the way
my VCS is version 6.1 running on Solaris!
 

Basically, you can not separate the vector like
m[100:90], you should use
wire [11:0]x=m[100:90];

then use m[x-1:0]
 

debussy1765 said:
Basically, you can not separate the vector like
m[100:90], you should use
wire [11:0]x=m[100:90];

then use m[x-1:0]

Hi debussy1765

Would you pls give me a complete example
I dont understand the statement

wire [11:0]x=m[100:90];

would you pls explain more detail ?
 

guy, it's easy.

do like this.

reg [127:0] temp;

temp = chip.mem;
data={temp[127:63],temp[127:63]} ;

have a try.
 

billjoy said:
it's a simulation model,
two dimension array can let simulate more convinence

it's inside a task :
//===========

reg [32:0]mem[127:0];
reg [127:0]databuf;

task a;
input
output
int i;
begin i=0
@(.....)
repeat(33) begin
databuf={chip.mem[127:63],chips.mem[127:63]} ;
$display("...%h..............".databuf);
.........
end
i=i+1;
...
end
endtask

//===========use VCS






Hi, you define the type databuf as a 128-bit variable(register); however you assign a vector to this scalable varialbe. I think you maybe made a mistake in your coding.


The accessing width of the memory is 128bit or as you defined 32-bit?


For the assignment mechansim, please refer to the extension of verilog2001
 

If you had a later VCS version, using SystemVerilog mode when you compile, would allow your code.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top