Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

max length of the ddr2 address signals

Status
Not open for further replies.

ITing

Newbie level 3
Joined
May 11, 2004
Messages
4
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
40
ddr2 burst

Hi,everyone
I want to write a ddr2 controller in VHDL.
Now, there is a problem in front of me.It is burst length.
In JEDEC standard its value is 4 or 8. when it's 4, it means if you write a data in location0 the location 1,2,3 in the same columne will be assert one by one.The data keep in the location 1,2,3 would be overwrite. How can i keep data safe? The length of data i will write is not fixed, but in byte.

thanks.
 

ddr2 burst length

Hi.I am writing a SDRAM's controller.
Maybe you can make some special area to store your data respectively,set some counters to store the data's address in turn.
 

    ITing

    Points: 2
    Helpful Answer Positive Rating
burst length ddr2

Use the MASK in the write operation. -> Examine DM input in the JEDEC specification.
 

    ITing

    Points: 2
    Helpful Answer Positive Rating
burst length4 in ddr2

If it is a component, DM is a good choice.But as i know, in DIMM package, DM is usually connected to VSS by mannufacture. Such as HTJ36C512x72G from micron.
:cry:

Added after 11 minutes:

chrometta said:
Hi.I am writing a SDRAM's controller.
Maybe you can make some special area to store your data respectively,set some counters to store the data's address in turn.

You mean i can store a 4/8xbus_width data first, and then wirte them in one write command.That is a good idea.
But, when the address is not sequential, i think, it maybe can't work well.:cry:
 

burst length 1 2 4 8

DM inputs doesn't connected to the ground (Vss) in DIMM. I suppose you made such a decision based on the Functional Block Diagram (from HTJ36C512x72G specification)...

I think it will be useful for you to download this doc:
https://download.micron.com/pdf/technotes/ddr2/TN4703.pdf (page 7).

DM arn't independent inputs, but they multiplexed with DQS signals.

I hope it helps.
 

dd2 burst length

Thanks maksya!
You are right.
"If RDQS is disabled, DQS0-DQS17 bacome DM0-DM8 and DQS9#-DQS17# are not used." This description is found in HTF9C32_64_128x72 datasheet. And in the functional blcok diagram the DM is not connected to Vss also.

But, i am not sure if HTJ36C512x72G is the same. Why its datasheet don't mention it? Is it different?
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top