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The CPLD initial is invalid?how to initial the input signal?

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My design is a shift register ,and the input signal is SCL and SDA , the output is the shift register , i am initial the register ,but in real circuit , the initial value is not my want? the follow is my design project,who can help me? modify the file and upload to me?
 

Re: The CPLD initial is invalid?how to initial the input sig

help me ! i need you help very much!
 

You uploaded an entire Synplify+ISE project, and gave very little explanation.
You need to better isolate the problem and ask clear specific questions.
Remember, we don't have your hardware, and many of us don't have your tools.
 

Re: The CPLD initial is invalid?how to initial the input sig

i am sorry .i already upload the project but don't see here today.
i used the ISE 6.2 and synplify8.1 pro, the CPLD is xcr3064xl,
if i don't assign the shift data to the control data ,the design is work good,
Code: 
always @ (posedge wComplete)
begin
            rSelRxd = wCtrlData[2 : 0];
            rSelTxd = wCtrlData[5 : 3];   
            rSelRts = wCtrlData[8 : 6];
           rSelCts = wCtrlData[11 : 9];
 	 //   rSelDsr = wCtrlData[17 : 15];     
   	 	rSelDtr = wCtrlData[14 : 12];	 	
    //	rSelRi  = wCtrlData[20 : 18];
     //	rSelDcd = wCtrlData[23 : 21];
end

i dont know why this block execute while power on?i already initialize the wComplete to 0  in initial block.and the other block is the same.
i have another problem.	
when i constraint the MobRxd and MobTxd sign to 31 and 32 pin then the project cound not compile passed ,why? very thank for you help!
 

Re: The CPLD initial is invalid?how to initial the input sig

why do not i upload the file?
 

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