generate programming file - failed timing constraint

Hello, I bought a Analog devices board with xilinx fpga which is a deserialzer, used with their A/D eval boards And they gave me the code on the fpga as well. It had 3 modules and one UCF file, .npl file ( along with the .bit and .mcs file which were loaded) Now I opened this project in ISE 7.1 and it told me that it automatically converts the npl to ise format with this new version. I just did a very crude test after I opened the project( it contained the 3 modules and the ucf file) I hit "Generate programming file" and it generated the .bit file but I found there are 4 failed constraints ?

*TS_ADI_Clocking_inst_rxclkdcm_p=PERIODTIMEGRP"ADI_Clocking_inst_rxclkdcm_p" TS_dco_p PHASE 0.465 ns HIGH 50% 2.380ns 2.514ns 1

*TS_ADI_Clocking_inst_rxclkdcm_n=PERIODTIMEGRP "ADI_Clocking_inst_rxclkdcm_n" TS_dco_p PHASE 1.656 ns HIGH 50% 2.380ns 2.454ns 1

*OFFSET = IN 0 ns VALID 1.19 ns BEFORE COMP "dco_p" 0.000ns 1.500ns 3

*TIMEGRP "negedge_input_pads" OFFSET = IN-1.19 ns VALID 1.19 ns BEFORE COMP "dco_p" TIMEGRP rxclk_n_grp -1.190ns 0.051ns 3

What does this mean in general...I am kinda new and am just trying to learn what goes on that chip and how its done. I am trying to write a testbench and see the simulation in varios stages. so can anybody give me like a short how/what-to-do on this ? thanks much

Try examining the detailed timing report. In Project Navigator click:
-> Implement Design
-> Place & Route
-> Generate Post-Place & Route Static Timing Report
-> Text-based Post-Place & Route Static Timing Report
or
-> Post-Place & Route Static Timing Report
or
-> Analyze Post-Place & Route Static Timing (Timing Analyzer)

That should give you details of the worst offenders. A good starting place.

Is that Analog Devices project available for download somewhere?

thanks ! I am having a look at the timing report and the timing analyzer.
No its not available for download but they had sent me all the files so that I could modify them. I could email you the files. thanks again !

Try examining the detailed timing report. In Project Navigator click:
-> Implement Design
-> Place & Route
-> Generate Post-Place & Route Static Timing Report
-> Text-based Post-Place & Route Static Timing Report
or
-> Post-Place & Route Static Timing Report
or
-> Analyze Post-Place & Route Static Timing (Timing Analyzer)