+ Post New Thread
Results 1 to 7 of 7
  1. #1
    Member level 4
    Points: 1,962, Level: 10

    Join Date
    Mar 2004
    Location
    GREECE
    Posts
    71
    Helped
    2 / 2
    Points
    1,962
    Level
    10

    abo adc edaboard

    I am designing a Pipeline ADC (VDD=1v, Resolution 8 bit, F=15MHz) .
    The Opamp which i intend to use is a two stage differential Opamp. The input stage is a folded cascode and the second is a simple source follower which offers rail to rail output.

    My questions are the following: What is the necessary input Common Mode Range of the Opamp in order the ADC work properly. Also what kind of simulations (except AC for gain and phase and DC) do i have to do in the Opamp (I suppose some transients) in order to verify its correct operation before i use it.

    Thanks

    •   AltAdvertisment

        
       

  2. #2
    Full Member level 1
    Points: 2,754, Level: 12

    Join Date
    Feb 2005
    Location
    Penang, Malaysia
    Posts
    102
    Helped
    6 / 6
    Points
    2,754
    Level
    12

    designing opamp for pipelined adc

    Hi,

    From my opinion, the Input common-mode range of your op-amp should be decided by the system requirement.

    You should run transient analysis for settling time of your op-amp. If you are running at 15MHz = 66.6ns full cycle, then your op-amp should settle within half clock cycle = 33.3ns to ensure your pipeline ADC works well. You should consider offset voltage as well. To find more I recommend you to read Masumi Abo thesis report from UC Berkeley. You should be able to find it using google search engine. Also try thesis report from Almea Delcaic from University of Maine. Just browse through the University EE department webpage and go to VLSI design. I have tried it before.! Hope it helps....all the best

    Don't forget to click the 'help' button

    regards,
    -snoop835-



  3. #3
    Advanced Member level 3
    Points: 7,066, Level: 20

    Join Date
    May 2004
    Posts
    874
    Helped
    69 / 69
    Points
    7,066
    Level
    20

    pipeline adc thesis

    Quote Originally Posted by moisiad
    I am designing a Pipeline ADC (VDD=1v, Resolution 8 bit, F=15MHz) .
    The Opamp which i intend to use is a two stage differential Opamp. The input stage is a folded cascode and the second is a simple source follower which offers rail to rail output.


    Thanks
    Would you mind upload the circuit?
    The source flower is diffictult to rail to rail output



    •   AltAdvertisment

        
       

  4. #4
    Member level 4
    Points: 1,962, Level: 10

    Join Date
    Mar 2004
    Location
    GREECE
    Posts
    71
    Helped
    2 / 2
    Points
    1,962
    Level
    10

    abo thesis

    Dear sunking

    Yes you are right. By mistake i wrote source follower instead of common source stage which is the correct.



  5. #5
    Full Member level 3
    Points: 2,866, Level: 12

    Join Date
    Jul 2004
    Posts
    160
    Helped
    15 / 15
    Points
    2,866
    Level
    12

    design of pipeline adc

    Quote Originally Posted by snoop835
    Hi,

    From my opinion, the Input common-mode range of your op-amp should be decided by the system requirement.

    You should run transient analysis for settling time of your op-amp. If you are running at 15MHz = 66.6ns full cycle, then your op-amp should settle within half clock cycle = 33.3ns to ensure your pipeline ADC works well. You should consider offset voltage as well. To find more I recommend you to read Masumi Abo thesis report from UC Berkeley. You should be able to find it using google search engine. Also try thesis report from Almea Delcaic from University of Maine. Just browse through the University EE department webpage and go to VLSI design. I have tried it before.! Hope it helps....all the best

    Don't forget to click the 'help' button


    regards,
    -snoop835-
    dear snoop835,
    i have searched thje papers told by you but all in vain.can you tell me what is the exact steps in google i should perform to search for these thesis.



    •   AltAdvertisment

        
       

  6. #6
    Full Member level 1
    Points: 2,754, Level: 12

    Join Date
    Feb 2005
    Location
    Penang, Malaysia
    Posts
    102
    Helped
    6 / 6
    Points
    2,754
    Level
    12

    pipelined adc design report




  7. #7
    Advanced Member level 1
    Points: 3,359, Level: 13

    Join Date
    May 2004
    Location
    China
    Posts
    422
    Helped
    24 / 24
    Points
    3,359
    Level
    13

    op amp before adc input

    Actually, you don't need the cascode opamp as input, ordinary two-stage opamp is enough for your specs.



--[[ ]]--