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Opamp design for Pipeline ADC

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moisiad

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abo adc edaboard

I am designing a Pipeline ADC (VDD=1v, Resolution 8 bit, F=15MHz) .
The Opamp which i intend to use is a two stage differential Opamp. The input stage is a folded cascode and the second is a simple source follower which offers rail to rail output.

My questions are the following: What is the necessary input Common Mode Range of the Opamp in order the ADC work properly. Also what kind of simulations (except AC for gain and phase and DC) do i have to do in the Opamp (I suppose some transients) in order to verify its correct operation before i use it.

Thanks
 

designing opamp for pipelined adc

Hi,

From my opinion, the Input common-mode range of your op-amp should be decided by the system requirement.

You should run transient analysis for settling time of your op-amp. If you are running at 15MHz = 66.6ns full cycle, then your op-amp should settle within half clock cycle = 33.3ns to ensure your pipeline ADC works well. You should consider offset voltage as well. To find more I recommend you to read Masumi Abo thesis report from UC Berkeley. You should be able to find it using google search engine. Also try thesis report from Almea Delcaic from University of Maine. Just browse through the University EE department webpage and go to VLSI design. I have tried it before.! Hope it helps....all the best

Don't forget to click the 'help' button :)

regards,
-snoop835-
 

pipeline adc thesis

moisiad said:
I am designing a Pipeline ADC (VDD=1v, Resolution 8 bit, F=15MHz) .
The Opamp which i intend to use is a two stage differential Opamp. The input stage is a folded cascode and the second is a simple source follower which offers rail to rail output.


Thanks
Click to expand...

Would you mind upload the circuit?
The source flower is diffictult to rail to rail output
 

abo thesis

Dear sunking

Yes you are right. By mistake i wrote source follower instead of common source stage which is the correct.
 

design of pipeline adc

snoop835 said:
Hi,

From my opinion, the Input common-mode range of your op-amp should be decided by the system requirement.

You should run transient analysis for settling time of your op-amp. If you are running at 15MHz = 66.6ns full cycle, then your op-amp should settle within half clock cycle = 33.3ns to ensure your pipeline ADC works well. You should consider offset voltage as well. To find more I recommend you to read Masumi Abo thesis report from UC Berkeley. You should be able to find it using google search engine. Also try thesis report from Almea Delcaic from University of Maine. Just browse through the University EE department webpage and go to VLSI design. I have tried it before.! Hope it helps....all the best

Don't forget to click the 'help' button :)


regards,
-snoop835-
Click to expand...

dear snoop835,
i have searched thje papers told by you but all in vain.can you tell me what is the exact steps in google i should perform to search for these thesis.
 

op amp before adc input

Actually, you don't need the cascode opamp as input, ordinary two-stage opamp is enough for your specs.
 

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