Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

muxed flip-flop scan chain insertion question

Status
Not open for further replies.

qjlsy

Member level 3
Joined
Apr 26, 2004
Messages
63
Helped
1
Reputation
2
Reaction score
1
Trophy points
1,288
Activity points
653
scan chain insertion

Hi, I tried a test for muxed flip-flop scan chain insertion, but I met a DRC violation as following:

Warning: Input force of chain c0 must be loaded by first cocking of in_reg1_reg (S6-1)

1 Invaild force scan input time violation.

This DRC violation ocurred after dft_insert. Before insertion no violation reported. And no sequential cell violation reported in the whole session.

1. What cause this violation? Incorrect initial potocol? Or incorrect test clock waveform?

2. How can I get the value of test clock's period? It's in target library, right? How can I read it out?

3. Log file said, set_test_hold value for asynch. rst_b signal is ignored. Why? Is this setting no need for muxed flip-flop scan style? I remember sysnopsys document said this kind of signal of a cell need to be configuared by asynch & test_hold.

Thanks a lot!
 

scan timing library

qjlsy said:
Hi, I tried a test for muxed flip-flop scan chain insertion, but I met a DRC violation as following:

Warning: Input force of chain c0 must be loaded by first cocking of in_reg1_reg (S6-1)

1 Invaild force scan input time violation.

This DRC violation ocurred after dft_insert. Before insertion no violation reported. And no sequential cell violation reported in the whole session.

1. What cause this violation? Incorrect initial potocol? Or incorrect test clock waveform?

I assume your using the DFTCompiler-Tetramax flow.
Most probably in your test protocol. Check your spf file to make sure that primary inputs can change before your clock changes.
Sometimes the test protocol file from DFT compiler needs to be hacked for Tetramax to work. Ask your Synopsys AE if this is the case.

qjlsy said:
2. How can I get the value of test clock's period? It's in target library, right? How can I read it out?

Should be in your test protocol file (spf file), if you have written it out from DFTcompiler. This number is usually a bogus number that has nothing to do with the actual library delays. If you want to find how fast your scan can run, you need run STA.

qjlsy said:
3. Log file said, set_test_hold value for asynch. rst_b signal is ignored. Why? Is this setting no need for muxed flip-flop scan style? I remember sysnopsys document said this kind of signal of a cell need to be configuared by asynch & test_hold.

Thanks a lot!

I believe set_test_hold is required is some stages of DRC checking but not all. At which step did the tool report that it is not needed?
One way to tell if it is really not needed is to remove this from your script and rerun scan insertion. If it does not produce the same result, you know it is needed.
 

scan flipflop

Dear dr_dft,

3. set_test_hold value for asynch. rst_b signal is ignored from the beginning creating protocol to the last dft_drc after insert_dft.

I tried as you said, removing set_test_hold for rst_b. The result of rerun is the new script produced the same result!!! And this time, no warning about "Ignoring".

So it doesn't need, right? Just doesn't muxed flip-flop style need configuration for asynch. signal? Or don't other styles need care about asynch. signal either?

2. In your words, test clock period "Should be in your test protocol file (spf file)"

(1)I can't see it in spf file.
(2) You said, run STA to get the real test clock period. Then what is the next step to do to set test clock period?

I once set period for test clock, but dc told me "Error: Value for period is different from the default value specified by test_default_period/custom test protocol(UID319)"

That's the reason why I am curious about how to set test period for test clock. If no period is set, what meaning will -waveform option have?

1. You said, "Check your spf file to make sure that primary inputs can change before your clock changes. "

I check spf file. But I don't see any section about setting primary inputs change before clock changes. Which section is for this setting? Whether or not is without such a section the cause of the warning?

Thanks a lot! I much appreciate you! :|
 

scan insertion

Question 2, I have solved. I have got test clock period. :)
 

signal should be muxed in scan

qjlsy said:
Dear dr_dft,

3. set_test_hold value for asynch. rst_b signal is ignored from the beginning creating protocol to the last dft_drc after insert_dft.

I tried as you said, removing set_test_hold for rst_b. The result of rerun is the new script produced the same result!!! And this time, no warning about "Ignoring".

So it doesn't need, right? Just doesn't muxed flip-flop style need configuration for asynch. signal? Or don't other styles need care about asynch. signal either?

In DFT Compiler, I believe if you did
set_signal_type -test_async_inverted rst_b
then you don't need to set_test_hold.

qjlsy said:
-
1. You said, "Check your spf file to make sure that primary inputs can change before your clock changes. "

I check spf file. But I don't see any section about setting primary inputs change before clock changes. Which section is for this setting? Whether or not is without such a section the cause of the warning?

Thanks a lot! I much appreciate you! :|

You should have a section that lists your inputs, outputs, inouts, and clocks, and have a timing label to point to the waveform table. The input waverform is usually defined as _default_In_Timing_ in the waveform table.
If this is missing, this could be a source of your S6 warning.
 

muxed flip flop

3.
a.You should use the following command to rst_b without set_test_hold command on rst_b
set_signal_type -test_async_inverted rst_b

b.You can leave the rst_b without constraint. i.e.,neither set_signal_type nor set_test_hold command is applied to rst_b, DC can recognize rst_b as async_inverted
signal.

But why set_test_hold need not be set?
If you study the spf files generated, you can see that there is a capture block about rst_b just like test_clock if you set_signal_type -test_async_inverted or no command is applied on rst_b. i.e., during test , rst_n can be pulsed.
While if you use set_test_hold, capture block about rst_b will be lost because this signal cannot be pulsed during test.
So you can lost test coverage if you set_test_hold on rst_b.

Good Luck
Claint
 

scanning flip flop

Question 1 is still NOT solved!!!

I checked spf file. Timing section and waveform table exsits.

I read synopsys document and found following sentence:

"after insert_dft, the initialization sequence is lost. You must reapply the same initialization sequence to ensure that post-scan insertion test DRC reports no violations."

Yes, in my question 1, the violation ocurred only at the last dft_drc, which is after insert_dft. And original warning prompt "Warning: Input force of chain c0 must be loaded by first cocking of in_reg1_reg (S6-1)" just complains that test_si/primary input need to be load before 1st clock.

How should I modify my script? I just set test clock, async. rst, and scan enable attribute for design. Then insert scan. Is there any other steps need to be done? reapply test_setup? How to? Or need to add patterns in spf?

But why everything is right for dft_drc before insert_dft?

Could somebody give me some help?

Thanks a lot!

Added after 53 minutes:

I got it, finally! :D

Now everything is ok, and the log file looks so beautiful! Have a nice day! :D
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top