qjlsy
Member level 3
scan chain insertion
Hi, I tried a test for muxed flip-flop scan chain insertion, but I met a DRC violation as following:
Warning: Input force of chain c0 must be loaded by first cocking of in_reg1_reg (S6-1)
1 Invaild force scan input time violation.
This DRC violation ocurred after dft_insert. Before insertion no violation reported. And no sequential cell violation reported in the whole session.
1. What cause this violation? Incorrect initial potocol? Or incorrect test clock waveform?
2. How can I get the value of test clock's period? It's in target library, right? How can I read it out?
3. Log file said, set_test_hold value for asynch. rst_b signal is ignored. Why? Is this setting no need for muxed flip-flop scan style? I remember sysnopsys document said this kind of signal of a cell need to be configuared by asynch & test_hold.
Thanks a lot!
Hi, I tried a test for muxed flip-flop scan chain insertion, but I met a DRC violation as following:
Warning: Input force of chain c0 must be loaded by first cocking of in_reg1_reg (S6-1)
1 Invaild force scan input time violation.
This DRC violation ocurred after dft_insert. Before insertion no violation reported. And no sequential cell violation reported in the whole session.
1. What cause this violation? Incorrect initial potocol? Or incorrect test clock waveform?
2. How can I get the value of test clock's period? It's in target library, right? How can I read it out?
3. Log file said, set_test_hold value for asynch. rst_b signal is ignored. Why? Is this setting no need for muxed flip-flop scan style? I remember sysnopsys document said this kind of signal of a cell need to be configuared by asynch & test_hold.
Thanks a lot!