How to run simulation with mixed-signal design?

My design include analog part and digital one, since analog part is schematic and digital one is verilog netlist, how should I run simulation? Someone said there's two way, one is run in dracula and the other, run v2lvs to convert verilog to spice netlist and then run simulation, but I don't know the details, who may give one detailed explanation? Thanks for your help!

Which flow do you take? In synopsys, you can use nanosim .

You can use nanosim or hsim

Basically, you have several method to simulate the mixed-signal design.

- If your digital design is very small you can run it in the HSpice / nanoSim or Ultrasim. In such a case you will have to use to transistor standard cell library.

- If your digital design is very big, it seems that you could not get it done in HSpice, you have to simulate it in a digital simulator. In such a case the behavioral model is used to describe the analog module. However, if your behavirial model is not fully verified, it will bring some troubles to you.

- Therefore, now most EDA tool vendors provide a mixed-signal simulation flow that could combine your digital simulator and your analog simulator together. An example is Synopsys could combine the VSS and nanosim/Hspice.

If you have a clear SPEC, and your design is large, just use behavioral description of analog module. Mixed use of analog and digital simulator is not widely used. But in the case you have no other way to check some cases in the digital part or the interface between the analog and digital, use this way is a good choice.

use nanosi + vcs to implement it.

You also can use hsim + ncsim