Why SOI technology is preffered for RFIC design?

body snatcher bicmos

Hello All

Anyone has any idea why SOI technology is preffered for RFIC design?
Kindly share with me any good links on this topic especially in the area of RFIC
Thank you so much

best regards
Jason

Re: SOI for RFIC

I believe you are over optimistic about SOI. You need to read the recent issues or volumes published in 2004 and 2005 by IBM on expert advice when using SOI for RFIC or Microwave Circuits.

SOI was used primarily in space engineering since mid-70s when IBM innovated this technology because it offers several advantages than other technologies such as Bipolar and CMOS because it minimises the bulk capacitance to enhance speed or higher frequency response. SOI also minimises bulk leakage, thus extremely favourable for then solar and battery-operated space devices of the 70s.

Cost is the key reason why SOI is still not the mainstream technology for RFIC.
SOI even today cannot eliminate substrate coupling problem.

IBM Microelectronic Division cannot guarantee 100% success to control the preparation for SOI substrate. It is extremely difficult to create Silicon epitaxy over Silicon Dioxide, especially when designers want a very thin layer. In reality, to create a uniform grain of Silicon epitaxy, the layer oftens turn out rather thick to actually become marginally satifactory. This thick Silicon epitaxy provides undesirable avenues for substrate coupling because dopings at source and drain are usually shallow. The bulk underneath these dopings are such avenues.

Re: SOI for RFIC

Dear SkyHigh

Thank you so much for posting the idea.
I am surprised to hear that. I thought soi will become the mainstream or is already the mainstream.
Kindly let me know where can I see the latest issue of published by IBM expert?

And for the creation of soi substrate, any sites or good link or even book you can recommend?

So do you forsee SOI technology will soon be replaced or challenged by other technology?
By the way, are there any other technology that is emerging ?

Thank you so much

best regards and thanks
Jason

Re: SOI for RFIC

You could read IBM journals at https://www.research.ibm.com/journal/rd46-23.html
or
most specifically read this paper published by IBM TJ Watson Laboratory Leading Researcher Dr Ning
www.research.ibm.com/journal/rd/462/ning.pdf

IBM researchers collobratively published a hot-selling book on BiCMOS SOI SiGe bible just last year in early 2004 that also includes their latest breakthrough in BiCMOS SOI substrate SiGe Graded Base HBT Transistor in August 2003. I think it is on sale on Amazon.

From the above material, you can find most of the information you need to know more about SOI.

The biggest challenge for SOI is still cost and quality of SOI substrate.

Cost favours CMOS, this a sure thing every expert will tell you. If you read carefully enough or always keeping abreast in track with the latest development over the past 5 years, CMOS keeps pushing the frequency limitation beyond 20, 40, then 65 GHz barrier and this was broken last year. People are already working with 95 GHz CMOS RFIC. Slowly what was established and stablised work in GaAs are re-implemented in CMOS, with the help of strained SiGe of course.

Device and Voltage Scaling, and Substhreshold Ultra-low-power are other 2 factors that favour CMOS.

SOI and GaAs used to beat CMOS in speed, perhaps SOI is much better than GaAs to offer low noise, but GaAs beats SOI in lower cost. But none beats CMOS in extremely cost.

To replace CMOS totally is an impossible mainstream to turn the tide over. I see SOI and GaAs getting replaced by CMOS instead. In fact, this is happening now.

GaAs itself already lost it's importance in photonic devices. Cheap LEDs use GaP(N). Lasers uses GaN. Infra-red diodes might still use some GaAs.

Even GaAs microwave devices are slowly changing back to SiGe CMOS.

Even nanotechnology in Ballistic Transport and Carbon Nanotube might not even replace CMOS in the next 5 to 10 years.

Re: SOI for RFIC

I have worked on RFIC's on SOI, so I can give you my 2cents, although I'm not a process expert.

The basic BJT or MOS used in SOI is not that much better then a non-SOI device with the same channel features, however, there are things that SOI allows that is very helpfull for RF chips.

The first is the fact that SOI doesn't suffer from latchup. This is very important when trying to maximize efficiency and you use inductors that have signals ride on top of the supply. In a normal process, this would result in latchup and body diodes turning on since your signal path goes above the supply. At >1GHz speeds, you can't build a body-snatcher type circuit that could follow your output signal and charge up all the wells that need it, and even if you could, that would result in a very high loading.

The second advantage is shared with most isolated processes: you can bias the body of any MOS to whatever you want. This allows for some very linear circuits.

The last advantage is that the substrate can be made very resistive since you're not growing devices on it, which results in lower substrate losses when designing inductors and such. This however is a complicated issue because of imperfections. The problem is that the oxide layer can cause an inversion at the silicon subtrate. What this means is that above and below the oxide, you can create a conductive layer that helps create a very good coupling mechanism for RF signals. The oxide is fairly thin and is over a big area so although the DC resistance is almost infinite, the RF signals couple right through it. This was responsible for killing many chips and is a quality issue. I'm not sure if all wafer manufacturers have this problem when creating the oxide layer, but ours certainly had.

Greg

Re: SOI for RFIC

Greg, I didn't expect you to explain in details to him. Haha!

But I agree with Greg and to highlight again, it is the substrate coupling problem in SOI and quality of SOI substrate (better means higher cost).

Just to add further on substrate coupling when Greg mentioned the RF signal coupling through the oxide. While DC resistance is infinite for a thin oxide layer, however at very high frequencies (basically AC signals) this thin oxide layer (a capacitor) exhibits lower reactance as we all know Xc = 1/jwC, resulting a very low impedance for RF signals to couple through this oxide layer.

I wish to highlight the key issue is that your RFIC chip may get better performance (although some MNCs like Atmel claimed 40% better) but usually involve the use of very high quality SOI substrate, i.e. very expensive one. From research viewpoint, everyone wants to set a new record like playing Olympics. From market viewpoint, if you have to spend 10 times the price for the SOI substrate but getting 40% better in performance, you are asking for dismissal or demotion from office the next day by your boss. The worst scenerio is that you might not even get 40%! You might run into bad luck getting nothing out because this is not digital ICs like memory chips. This is RFIC which usually fail the first pass and most RFICs succeed after 2 or more passes in fabrications.

Re: SOI for RFIC

Dear Sky High and Greg

Thank you so much for explaining things in a comprehensive way for a newbie like me.
I am really getting so much helpful hints from this discussion
I will message you guys after I do some further reading
Thank you!

best regards
Jason

Re: SOI for RFIC

I believe SOI will be mainstream after 45nm. Thats what I have been told by my device team who used to work @ TSMC

Re: SOI for RFIC

45nm or any device scaling has nothing or very little to do with SOI. Down-sizing of gate lengths affect only the MOS devices itself, in turn the CMOS technology for digital VLSI/ULSI.

Dr Ning, a renowned researcher of IBM TJ Watson, has already forseen with other renowned experts in semiconductors that SOI sees importance only in high performance RF and Analog IC which will predominantly hover around 0.18 to 0.13 micron in the next 3 to 5 years. SOI not only failed to become a mainstream when SiGe comes into the picture.

When it comes to RF and Analog, down-sizing of devices besides increasing speed, it doesn't improve other performance metrics, thus increase resistance and thus noiser which is always a challenge in RF-Analog.

Re: SOI for RFIC

Yep I agree with SkyHigh. Currently @ 90nm companies are still able to take advantage of bulk CMOS as evident from recent Marvell and Intel sucess in WLAN RF transceiver design. But further downscaling as highlighed by SkyHigh, not much advantage is gained for Analog/RF circuitry. But since Analog/RF moves along with digital, for SOC, CMOS SOI may be a promising solution.

So, which is more likely to become mainstream, CMOS or BiCMOS SOI?

Re: SOI for RFIC

There was a period of time when electronic packaging consortium discusses about SOC, SIP and SOC hosted by Gatech (USA), IMEC (Belgium), KTH (Sweden) and other leading research groups. Prof Rao Tummala and Dr Laskar, both from Gatech gave alot of talks on this.

SOC is not a promising solution anymore due to high mask cost, NRE, test difficulty, subtrate coupling, IP reuse issues, hotspots, heat dissipation issues and etc. SOC byfar work alright with CMOS-based WLAN and Bluetooth chips due to relaxed IP issues and design compatibilities that are established over the past 15 years. SIP and SOP are becoming more cost-effective, less IP issues and reliability. There is a growing support for SOP and SIP instead. The reason being that not everything can fit into SOC unless it favours cost, IP and performance issues.

CMOS still remain the dominant technology for Digital. BiCMOS sees potential in RF-Analog due to matching and linearity is better in Bipolar, especially the case for RF, whereas Analog can fit well in CMOS. SOI sees purposes in RF.

Unless CMOS fails to go beyond some hundreds of GHz, and someone marvelously creates a low cost SOI substrate, SOI will still find hard to replace or rival with CMOS.

Re: SOI for RFIC

SOI though became mainstream in processors. All high performance processors now use 90nm SOI with strained silicon.

Re: SOI for RFIC

Very excellent discussion. I gain a lot from this forum
Anyone has idea which company or product is using soi cmos for rf application and has proven its low noise feature but able to manufactured at low price(for its substrate or control of buried oxide)?

One silly question, processor is running at high speed and for example like centrino technology which deals with wireless connection. So can it be considered as part of rf application? Is it using soi?

Kindly advise

Thank you

Jason

Re: SOI for RFIC

ocarnu,

A question to ask would be, "who are the makers of SOI-based processors?", and you will know who can afford the investment and who can mass-produce to reduce the selling price per chip. Besides seeing IBM for their supercomputers, AMD for their Athlon and Hammer series, do you see big players?

SOI indeed has several advantages over bulk silicon for CMOS that we know:
1. Static and Dynamic Power Reduction
2. Noise Reduction

Every semiconductor companies love to have SOI, but simply can't offer. To make it a mainstream for very big players, that's fair enough, not for the global electronic community where many medium to small semiconductor companies can't play. So how can SOI become a mainstream when not everyone can play?


jason_class,

You may check Honeywell, RFMD and Atmel for SOI-based RF components. They are leading players in Microwave and RF devices.

Intel Centrino does not use SOI technology. Intel focuses on using low-K interconnect as their aim to reduce power consumption as principly cutting driving effort cuts power.

AMD visions to improves chip performance by using new substrate like SOI.

They are competitors, just using different approach to achieve similar goals - high performance, low-cost and reliable chips.

No, not RF applications. Still within the domain of high-speed digital systems at GHz frequencies. To be specific, IEEE specially called this the GHIC or Gigahertz Integrated Circuits that encompasses ICs of digital, analog and RF domain operating in the GHz range.

Re: SOI for RFIC

Thank you all

Thanks Ocarnu and Sky High for the comments.

So now people are going for fully or partially depleted SOI?
How people actually decide which type they would go for?

Anyone knows well about device physics for the two types?

Kindly share your opinion

Thank you all

best regards
Jason

Re: SOI for RFIC

Jason

Try reading " LOW VOLTAGE SOI CMOS VLSI DEVICES and CIRCUITS"by Kuo and Lin and SOI Technology by Colinge

Re: SOI for RFIC

Yes Srini
WIll check it out when there are copies in library
Thanks

Jason

Re: SOI for RFIC

Jason

Also check out "SOI Design concepts" . It has explanation of some basic SOI stuff like nand gate etc