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Design constraints at synthesis level

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Hello Freinds,

Here i have a new doubt, as i am not well experienced at synthesis level.

Here while giving constrains to a design at synthesis level, such as clock freq, input delay, output delay, flip-flop delay's etc, For clock freq it is well known according to the protocol frequency is the constrain, but what about the other delays such as inpu out put flipflop and other delays how do we measure and give.

Please help me out of these rustic question.

Thank you
 

synthesis add output delay

inputdelay : depends on external devices clk-to-output delay
output delay: depends on external devices setup time

use clock_uncertainty

use set_input_transition on input ports

use set_load on output ports

define proper false and multi-cycle paths

These are most important. utmost important are input and output Maximum and minimum delays.
 

    I

    incisive

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how to constrain a design

Input and output delays depend on whether you are synthesizing a block inside the chip or a full top level of the chip.
For internal block, the has to be some time budgetting to split the cycle time between the 2 blocks that are talking to each other. There are some floorplanning tools that can deal with this.
For chip level, it either comes from the spec of standards, like SRAM, PCI, etc., or you need to define your own spec that your customer can live with.
 

how to handle a wire_load

Thanks for giving the details,

But from when can we get the input and output delays, suppose for example there is module (usb) where we r synthezing the design, now where does the delays come from?
please clear me if i am wrong.

thank you.
 

    I

    incisive

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set output delay+synthesis

Refer multiple USB datasheets. And extract all timing parameters for different modes such as DMA read, DMA write, CPU read, CPU write..etc. For each mode, the timings will be given with respect to one reference signal.

set_max_delay on reference signal.

set_max_delay 16 [get_ports usb_rd_n]
set_min_delay 4 [get_ports usb_rd_n]

now define all input and output delays with respect to reference signal like,

ex: usb_dat need out setup time of 6ns and out hold time of 2ns with respect to usb_rd_n. then,

set_input_delay -max [expr [ 16 + 6]] [get_ports usb_dat]
set_input_delay -min -[expr [ 4 + 2]] [get_ports usb_dat]

Remember, this is an asynchronous interface. it very complicated.

for synchronous interfcaces, it is much simple as i told above.
 

driving cell+synthesis

set driving cell to input ports and wire load model

I have a question about driving cell and output loading.

how to determine driving cell , output loading and wire load model.

Thank you !
 

input and output delay in synthesis

use set_input_transition on input ports. Generally use 1ns per 1 volt, means for 3.3v TTL; set_input_transition 3.3 [all_inputs].

Note: exclude clock ports from above.

wire_load is determined by the size of each module u r synthesizing. for example, for 10K gate module, check ur foundry documentation for the wire laod model to be used. For each size and for top level check ur foundry docs for wire load selection. OR turn ON auto wire load selection in DC.

Generally set_load 35 [all_ouputs] -> LOAD on ooutput pors.

For more precise LOAD on out ports, check target device datasheet.
 

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