Diff between well contact and substrate contact in 90nano

Hi Guys
I am using tsmc 90 nano technology and i have a dought about the diff between substrate contact and well contact. In my schematic i have used mim capacitors and while generateing the layout for them it give me a well contact in the layout now i am confused where do i connect thsi.. because i also have a substrate contact.

Can you pls tell me where do i connect these 2 contacts..

Thanks in Advance
Tama

Re: Diff between well contact and substrate contact in 90nan

Hi,

I don't know the tsmc90 but if you have a well tie and a substrate tie for mim cap it seems to me that in this tekno there is nwell or dnwell under mim cap. I think you should have a pin for this well tie in your schematic too or in the properties. Also some deck have a special symbol to represent this tie to dnwell. It's up to you and your design to which net you have to connect this well. You propably need to cancel parasitic capacitance to substrate. Or if you don't need it there is also maybe an option or another mim cap device in the deck.
And for the substrate tie I think you know well why it's here!!
Hope it helps,

Franck.

Re: Diff between well contact and substrate contact in 90nan

Hi franck
Thanks for your reply. as you have mentioned in this tech i do have a dnw and it has a well contact option in its properties... this enable a well contact on its 4 sides..and as per that i have connected the well tie to it. But now the question is that where do i connect the substrate. I know why it is there. But the cell which i am using in that the nmos substrates is directly connected to vss hence there is no substrate connection to which i have to tie this pin. and if you talk about the mim cap then can you tell where do i connect the substrate pin in the layout..

thanks in adcance.
tama

Re: Diff between well contact and substrate contact in 90nan

Hi Tama,

"... the nmos substrates is directly connected to vss ...".
So you should connect the substrate tie of your mim cap to vss.

There is a lot of way to deal with DNWELL in a deck depending on each tech.
Some deck define the DNWELL, the internal substrate and the external substrate.
Some just define the DNWELL and the external substrate.
Some uses both depending on the devices.
Some uses pins in the schematic, some uses just properties, some uses both, some have a special diode cell to define the dnwell, the external substrate and the internal substrate ...

So what I want to say is you should be really carefull of how your deck deals with DNWELL just to be sure to not do silly mistakes.
Anyway in your case of the mim cap, I think you want a PLAIN DNWELL under the cap and so the substrate tie is just here to define the EXTERNAL substrate which is in your case the substrate of your NMOS so VSS.

Franck.

how can you construct your cap? which layers you used? It generate a well contact because in the techfile define well contact as you did, so i suggest you construct your cap as tsmc suggest, of course, if you sure you are right, you can modify the techfile, but it is dangerous