yxwang
Newbie level 1
Hi Everybody,
I would like to know, in term of the practical design issue, how should I deal with common-mode output values between open loop OTA with CMFB and open loop OTA without CMFB.
This is a one stage differential fold-cascode opamp design with CMFB.
Say, Case 1, if the VDD is 5 v, the common-mode output of this OTA normally has to be set with 2.5v with CMFB. So first when I did hand calculation (in rought) and put all transistors in the schematic (Cadence), and slightly adjust the sizing of the transistors and the simulation gave the following commom-mode output value without CMFB. Here, I only show one branch of the cascode stage:
(Without CMFB)
VDD
M1 (PMOS, 150um/1um)
M3 (PMOS, 150um/1um)
<----common-mode output sit at 500mv without CMFB
M5 (NMOS, 100um/1um)
M7((NMOS, 160um/2um)
GND
(WIth CMFB)
VDD
M1 (PMOS, 150um/1um)
M3 (PMOS, 150um/1um)
<----common-mode output sit at 2.495v with CMFB
M5 (NMOS, 100um/1um)
M7((NMOS, 160um/2um)
GND
( I use TSMC 0.5um 5v VDD), under this configuration, the M5 is in triode region.
Then, after I connected this OTA with CMFB, all transistors are in saturation region and I could clamp the output common-mode value back to 2.5v around (VDD/2).
Case 2: Same VDD and models, I adjusted the transistor sizing intensively and achieved the commom-mode output value from 2v to 3v or even somewhere around 2.5v without CMFB. Then after adding CMFB, the output common-mode value will also be clamped to 2.5v. All transistors in this case are in saturation in two configuration (with and without CMFB). But in this case, the aspect ratios for the transistors in the cascode stage do look that "neat". And I doubt in the industry these small variations for aspect ratios will not work due to process variation.
Case2: (Without CMFB)
VDD
M1 (PMOS, 163.3um/1um)
M3 (PMOS, 156um/1um)
<----common-mode output sit at 2.65v without CMFB
M5 (NMOS, 100um/1um)
M7((NMOS, 169um/2um)
GND
You see there is pretty much variations in the aspect ratios for those transistors. Do you think these variations are necessary?
So, which case is more practical? or None of them? or you think it doesn't matter with either one of these?
Or which design method (or way) goes in industry in term of this question (OTA with or without CMFB)? I would like to take some instruction on this.
Appreciate your help.
-yx
I would like to know, in term of the practical design issue, how should I deal with common-mode output values between open loop OTA with CMFB and open loop OTA without CMFB.
This is a one stage differential fold-cascode opamp design with CMFB.
Say, Case 1, if the VDD is 5 v, the common-mode output of this OTA normally has to be set with 2.5v with CMFB. So first when I did hand calculation (in rought) and put all transistors in the schematic (Cadence), and slightly adjust the sizing of the transistors and the simulation gave the following commom-mode output value without CMFB. Here, I only show one branch of the cascode stage:
(Without CMFB)
VDD
M1 (PMOS, 150um/1um)
M3 (PMOS, 150um/1um)
<----common-mode output sit at 500mv without CMFB
M5 (NMOS, 100um/1um)
M7((NMOS, 160um/2um)
GND
(WIth CMFB)
VDD
M1 (PMOS, 150um/1um)
M3 (PMOS, 150um/1um)
<----common-mode output sit at 2.495v with CMFB
M5 (NMOS, 100um/1um)
M7((NMOS, 160um/2um)
GND
( I use TSMC 0.5um 5v VDD), under this configuration, the M5 is in triode region.
Then, after I connected this OTA with CMFB, all transistors are in saturation region and I could clamp the output common-mode value back to 2.5v around (VDD/2).
Case 2: Same VDD and models, I adjusted the transistor sizing intensively and achieved the commom-mode output value from 2v to 3v or even somewhere around 2.5v without CMFB. Then after adding CMFB, the output common-mode value will also be clamped to 2.5v. All transistors in this case are in saturation in two configuration (with and without CMFB). But in this case, the aspect ratios for the transistors in the cascode stage do look that "neat". And I doubt in the industry these small variations for aspect ratios will not work due to process variation.
Case2: (Without CMFB)
VDD
M1 (PMOS, 163.3um/1um)
M3 (PMOS, 156um/1um)
<----common-mode output sit at 2.65v without CMFB
M5 (NMOS, 100um/1um)
M7((NMOS, 169um/2um)
GND
You see there is pretty much variations in the aspect ratios for those transistors. Do you think these variations are necessary?
So, which case is more practical? or None of them? or you think it doesn't matter with either one of these?
Or which design method (or way) goes in industry in term of this question (OTA with or without CMFB)? I would like to take some instruction on this.
Appreciate your help.
-yx
