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How to generate fast inverted clock from 3GHz clock?

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jdhar

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Fastest Inverter

Hi,

I am doing a school project which involves designing a 4-bit LFSR (one xor in the front that is fed from the last 2 FF's) using 0.18u in Cadence. The goal is to make it as fast as possible, without consideration of area or power. We decided to use C2MOS (Clocked CMOS) for our flip flop's, and have reached a clock speed of about 3 GHz. It seems like the inverted clock that is required for CMOS is now holding up the circuit from clocking faster. Are there any tips on how to generate an extermely fast inverted clock from the given clock? We are given a 25ps rise/fall time clock from an ideal pulse generator.

thank you, Jai.
 

Re: Fastest Inverter

-One way is to use cascaded inverters as in the book: Digital Integrated Circuits: A Design Perspective, page 206-210 (2nd Edn), if the output capacitance is large, this should speed up your clock_bar.
-Make the clock rise and fall time 10ps.
-Another way is to use a TSPCR, which eliminates the need to use an inverted clock for your FFs, this is on page 350.

Remember, use thin lines to reduce the capacitive loading, and never use poly as a wire. I had the same problem by the way using crappy 0.18u TSMC transistors, and my clock couldn't go over 3GHz, but I didn't do any of the above because I'm lazy. Good luck.
 

Fastest Inverter

Thanks for your reply. I can't make my clock rise time faster because I am given that as my input (25 ps rise/fall). If there is any way to buffer the clock to increase ther ise time maybe? Also, I tried TSPCR, and unfrotunately, it is very sensitive to device sizing, so it didnt' seem like there was much room for improvement compared to C2mos. Also, this is pre-layout simulation I am talking about. After layout is a different story. We are required to optimize before layout.
 

Re: Fastest Inverter

where do you put your FF? Do you need to consider setup time for your FF?
To reduce the clk delay, you can skew your inverter to favor the interested edge,
such as beta_ratio=10 or 0.1
 

Fastest Inverter

What do you mean by where do I put my FF? It is smiply 4 FF's connected in series with an XOR feeding the input to the first (feedback paths from the last 2 inverters). I need both edges, so i don't think what you said will work
 

Re: Fastest Inverter

I think you can use dynamic logic for FF, then you only need to care for one clk edge.
Also dynamic logic is faster than static logic
 

Re: Fastest Inverter

yes go in for pass transistor and domino logic ...get on with faster work.
 

Fastest Inverter

i think you'd better have a full-customered design.
 

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